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DC Blocker

Started by b2508 ●October 22, 2015
Hi all,

I am trying to implement this DC blocker in FPGA.

http://www.digitalsignallabs.com/dcblock.pdf

However, my signal after it is significantly reduced in amplitude. What is
the best way to cope with this? Also, do I need to use DSP48 block (xilinx
FPGA) for this multiplication with pole?
 
Thank you.
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Reply by b2508 ●October 22, 20152015-10-22
I am trying to implement the second filter on figure 2.

So y[n] = x[n]-x[n-1]+p*y[n-1]

I am not sure what function should this noise shaping be?
Instead of that I am only subtracting e(n-1) from the above equation prior
to quantization.


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Reply by b2508 ●October 22, 20152015-10-22
Also I am interested if there is a way to implement this in FPGA if your
samples are coming at each clock cycle (i don't know how you refer to this
in english, fpga is clocked at sample frequency maybe?)
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Reply by ●October 22, 20152015-10-22
Unless you are really constrained in terms of gate count I would recommend using full double precision in the recursive section. It's only slightly more expensive than noise-shaping and you won't have troubles with idle tones from the noise-shaping. Idle tones have a nasty way of only being detected by your customers after you are shipping product. 

Bob
Reply by b2508 ●October 22, 20152015-10-22
But how is this related to the fact that signal is low? I think it gets
low after differentiator part?
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Reply by ●October 22, 20152015-10-22
The signal after the differentiator is low if the input signal is much lower than Nyquist. But there is no quantization in the differentiation operation so that is not a problem. The problem is in the recursive part, due to the necessary quantization. 

Bob
Reply by b2508 ●October 22, 20152015-10-22
Ok, thank you, signal is much better when I increase signal frequency or
decrease bandwidth.

Does anyone know how to implement this in FPGA when data arrives at every
clock cycle? 
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Reply by robert bristow-johnson ●October 22, 20152015-10-22
On 10/22/15 3:15 PM, b2508 wrote:

> Ok, thank you, signal is much better when I increase signal frequency or
> decrease bandwidth.
>
> Does anyone know how to implement this in FPGA when data arrives at every
> clock cycle?
>


i imagine there is someone who knows how to do that and exchanges such 
knowledge for payment of some form.  (i'm not one of them.)


-- 

r b-j                  rbj@audioimagination.com

"Imagination is more important than knowledge."
Reply by Allan Herriman ●October 23, 20152015-10-23
On Thu, 22 Oct 2015 17:51:27 -0400, robert bristow-johnson wrote:


> On 10/22/15 3:15 PM, b2508 wrote:
>> Ok, thank you, signal is much better when I increase signal frequency
>> or decrease bandwidth.
>>
>> Does anyone know how to implement this in FPGA when data arrives at
>> every clock cycle?
>>
>>
> i imagine there is someone who knows how to do that and exchanges such
> knowledge for payment of some form.  (i'm not one of them.)



I gave the answer away for free in comp.arch.fpga :)

The trick is to use shift (which is free in an FPGA) and subtract (which 
is really quick in an FPGA) instead of using a multiplier (which incurs 
at least one clock of delay).

Regards,
Allan
Reply by gretzteam ●October 23, 20152015-10-23
>On Thu, 22 Oct 2015 17:51:27 -0400, robert bristow-johnson wrote:
>
>> On 10/22/15 3:15 PM, b2508 wrote:
>>> Ok, thank you, signal is much better when I increase signal frequency
>>> or decrease bandwidth.
>>>
>>> Does anyone know how to implement this in FPGA when data arrives at
>>> every clock cycle?
>>>
>>>
>> i imagine there is someone who knows how to do that and exchanges such
>> knowledge for payment of some form.  (i'm not one of them.)
>
>
>I gave the answer away for free in comp.arch.fpga :)
>
>The trick is to use shift (which is free in an FPGA) and subtract (which



>is really quick in an FPGA) instead of using a multiplier (which incurs 
>at least one clock of delay).
>
>Regards,
>Allan


I think you can shave off a storage element by some block diagram
manipulation if useful. Something like this:


                 |highpassoutput
                 |
                 |
         +-------+----high precision zone --------+
  input  |  ,-.  |  +--+        ,-.               |
  -------+-( - --'--+*k+-------- + .......|       |
         |  `+'     +--+        `+'       |       |
         |   |                   |        |       |
         |   |     +--------+    |      +-+-+     |
         |   |..|..|.trunc..|....|......| z |     |
         |      |  +--------+           +---+     |
         +------+---------------------------------+
                |
                |lowpassoutput
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