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Concurrent embedded systems

Started by Unknown December 8, 2015
I was wondering how many of you when sampling signals use two concurrent loops. First loop to do the sampling and the second for the DSP. You send the data between the two with a FIFO. I assume this is way faster than a straight through single loop. Of course FPGAs are ok for this but unaware if anybody does this on say two processors.
On Mon, 07 Dec 2015 21:53:47 -0800, gyansorova wrote:

> I was wondering how many of you when sampling signals use two concurrent > loops. First loop to do the sampling and the second for the DSP. You > send the data between the two with a FIFO. I assume this is way faster > than a straight through single loop. Of course FPGAs are ok for this but > unaware if anybody does this on say two processors.
It depends. Lots of modern microcontrollers have pretty sophisticated hardware handling of the ADCs -- so often the innermost "loop" is the hardware shoving stuff into memory via DMA transfers without software intervention. If I'm doing something time critical I'll often manage the ADC (or DMA) traffic with an ISR that queues things up for a DSP routine that's operating at a significantly lower rate than the ADC. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
On 12/8/2015 12:53 AM, gyansorova@gmail.com wrote:
> I was wondering how many of you when sampling signals use two concurrent loops. First loop to do the sampling and the second for the DSP. You send the data between the two with a FIFO. I assume this is way faster than a straight through single loop. Of course FPGAs are ok for this but unaware if anybody does this on say two processors.
I guess I'm not clear on what you mean by one or two loops. Do you mean processes? -- Rick
On Tuesday, December 8, 2015 at 8:54:04 PM UTC+13, rickman wrote:
> On 12/8/2015 12:53 AM, gyansorova@gmail.com wrote: > > I was wondering how many of you when sampling signals use two concurrent loops. First loop to do the sampling and the second for the DSP. You send the data between the two with a FIFO. I assume this is way faster than a straight through single loop. Of course FPGAs are ok for this but unaware if anybody does this on say two processors. > > I guess I'm not clear on what you mean by one or two loops. Do you mean > processes? > > -- > > Rick
Two parallel while loops which run independantly of each other (not on the same processor)
On Tuesday, December 8, 2015 at 8:05:08 PM UTC+13, Tim Wescott wrote:
> On Mon, 07 Dec 2015 21:53:47 -0800, gyansorova wrote: > > > I was wondering how many of you when sampling signals use two concurrent > > loops. First loop to do the sampling and the second for the DSP. You > > send the data between the two with a FIFO. I assume this is way faster > > than a straight through single loop. Of course FPGAs are ok for this but > > unaware if anybody does this on say two processors. > > It depends. Lots of modern microcontrollers have pretty sophisticated > hardware handling of the ADCs -- so often the innermost "loop" is the > hardware shoving stuff into memory via DMA transfers without software > intervention. > > If I'm doing something time critical I'll often manage the ADC (or DMA) > traffic with an ISR that queues things up for a DSP routine that's > operating at a significantly lower rate than the ADC. > > -- > > Tim Wescott > Wescott Design Services > http://www.wescottdesign.com
That's just one processor though is it not - it cannot be concurrent.
On Tue, 08 Dec 2015 08:26:05 -0800, gyansorova wrote:

> On Tuesday, December 8, 2015 at 8:54:04 PM UTC+13, rickman wrote: >> On 12/8/2015 12:53 AM, gyansorova@gmail.com wrote: >> > I was wondering how many of you when sampling signals use two >> > concurrent loops. First loop to do the sampling and the second for >> > the DSP. You send the data between the two with a FIFO. I assume this >> > is way faster than a straight through single loop. Of course FPGAs >> > are ok for this but unaware if anybody does this on say two >> > processors. >> >> I guess I'm not clear on what you mean by one or two loops. Do you >> mean processes? >> >> -- >> >> Rick > > Two parallel while loops which run independantly of each other (not on > the same processor)
Again, it depends. If you have that much of a need for speed, and you're not trying to do the job with some off the shelf multi-processor board (or multi-core processor), then the answer will probably factor into fast simple stuff and slower more complicated stuff. In that case, the fast simple stuff should go into a small FPGA, and the slower more complicated stuff (unless it's still too fast) should go in a processor. I _have_ done this sort of thing, before processor companies started moving this sort of functionality inside their microcontrollers and DSP chips. -- www.wescottdesign.com
On 12/8/2015 11:26 AM, gyansorova@gmail.com wrote:
> On Tuesday, December 8, 2015 at 8:54:04 PM UTC+13, rickman wrote: >> On 12/8/2015 12:53 AM, gyansorova@gmail.com wrote: >>> I was wondering how many of you when sampling signals use two >>> concurrent loops. First loop to do the sampling and the second >>> for the DSP. You send the data between the two with a FIFO. I >>> assume this is way faster than a straight through single loop. Of >>> course FPGAs are ok for this but unaware if anybody does this on >>> say two processors. >> >> I guess I'm not clear on what you mean by one or two loops. Do you >> mean processes? >> >> -- >> >> Rick > > Two parallel while loops which run independantly of each other (not > on the same processor)
Yes, I missed the part at the very end where you mention two processors. I'm not sure exactly what your question is. I have never used two processors to do a job like this. The critical issue is seldom processor performance, so both tasks being in the same loop is not a problem from a speed perspective. It is a problem if there is a difference in timing of the two (DSP is done every 10 samples), but even then a simple gate will handle that issue. Usually the critical issue is the jitter in timing of obtaining the ADC sample. But as Tim has said, this is often handled with hardware sample timing or even DMA. There are multicore processors plenty. I am sure someone, somewhere has needed to do the sampling with one processor and used the other for the non-critical timing stuff like the DSP. I just think this is not commonly needed as it is not so hard to do with one processor unless there is a *lot* of other stuff going on. -- Rick
gyansorova@gmail.com wrote:
> I was wondering how many of you when sampling signals use two > concurrent loops. First loop to do the sampling and the second for > the DSP. You send the data between the two with a FIFO. I assume this > is way faster than a straight through single loop. Of course FPGAs > are ok for this but unaware if anybody does this on say two > processors. >
Results will vary. There is also nothing to keep you from interleaving the two "loops" in one say, "while (1) ..." loop for a single processor. "Two processors" is slightly ambiguous; could be a dual-core in which case some things are still shared that you'll have to accommodate. You kinda want the sampling part to be something like DMA. Much also depends on the interface to the sampling hardware. A 'loop' could be behind a device driver facade. The way to know what works is to instrument the code with at least counters that are incremented to show when something is not right. -- Les Cargill
On Mon, 07 Dec 2015 21:53:47 -0800, gyansorova wrote:

> I was wondering how many of you when sampling signals use two concurrent > loops. First loop to do the sampling and the second for the DSP. You > send the data between the two with a FIFO. I assume this is way faster > than a straight through single loop. Of course FPGAs are ok for this but > unaware if anybody does this on say two processors.
Given the wide range of answers you're getting, and the puzzlement that accompanies them -- perhaps you could tell us more, or even what your real question is? -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
<gyansorova@gmail.com> wrote:

>> On 12/8/2015 12:53 AM, gyansorova@gmail.com wrote:
>>> I was wondering how many of you when sampling signals use >>> two concurrent loops. First loop to do the sampling and the >>> second for the DSP. You send the data between the two with >>> a FIFO. I assume this is way faster than a straight through >>> single loop. Of course FPGAs are ok for this but unaware if >>> anybody does this on say two processors.
>Two parallel while loops which run independantly of each other (not on >the same processor)
You can certainly do this. A major complication would be if you had to send data in both directions. If it's one direction only (from the first processor to the second processor) than the second processor can simply poll the first processor. If things get too hairy you would either need to write a sychronizaiton kernel, or buy (or I suppose, write from scratch) an RTOS. Depending on your total project flow, using an RTOS right off the bat might be wise. Steve