I am designing a board with a TMS320F2811 chip, and have the schematic done. I was about to start the layout but I wanted to ask if it can work to make a double layered board (i saw a similar thread a while back, but it didn't seem to answer this directly). I am only going to be using the SCI pins and the analog inputs, so routing should be feasible. I was thinking about laying a ground plane under the chip and then a core supply ring around that and a IO supply around that (C shapes, not complete circle) on the bottom layer, then decoupling capacitors on the bottom too right below their respective pins. Is this feasible (college student, just trying to save a buck on PCB manufacturing). Thank you, James
double layered bords
Started by ●April 13, 2005
Reply by ●April 13, 20052005-04-13
James Cotton wrote:> I am designing a board with a TMS320F2811 chip, and have theschematic> done. I was about to start the layout but I wanted to ask if it canwork> to make a double layered board (i saw a similar thread a while back,but> it didn't seem to answer this directly). I am only going to be usingthe> SCI pins and the analog inputs, so routing should be feasible. I was > thinking about laying a ground plane under the chip and then a coresupply> ring around that and a IO supply around that (C shapes, not complete > circle) on the bottom layer, then decoupling capacitors on the bottomtoo> right below their respective pins. Is this feasible (collegestudent,> just trying to save a buck on PCB manufacturing). > > Thank you, > JamesHello James, This is a question with a not so simple answer. Certianly you have the number of signals quite low, so routing them is not a real issue. But you have started thinking about the real problem. Namely can you get the power into the chip quietly. Most modern cpus have multiple power pins where each pin powers a different portion of the chip. So sometimes when you have improper decoupling, some functions in the chip work while others act "dodgy." You "c" rings just may work - just pour as much copper as you can and provide multiple decoupling caps. However any high speed design I would do would have at least 4 layers. Do you really need a custom board, or can you get an eval board and add on your stuff - either in a breadboard region or as a daughter board? IHTH, Clay
Reply by ●April 14, 20052005-04-14
I probably could start w/ an eval board, but this is being designed for an EEG system so needs to be isolated well. If I were to use an eval board I would have either have to build a board w/ a bunch of isolation amplifier (expensive part count) or an isolated ADC which would probably be fairly easy. However, half the fun is the design and layout and eventually I'll want to make my own version anyway, so I figured I might as well start that way - esp. w/ the low signal count. It will probably be working at fairly high frequencies to preprocess as much as possible b4 sending it to the computer. If I got enough caps underneath the thing would my chances be decent or am I more likely to get dodgy than not? Also, w/ regards to decoupling, I notice most of the schematics online for the eval boards show many caps of a handful of values - I know this is to get best filtering at various frequencies, but what is the optimal placement plan. One cap per pin, regardless of value, and try and space them out? One of each value at a couple of local star supplies? Even distributed between a power ring and large ground pour w/ the pins making connections to the power ring wherever convenient? Thanks, James On Wed, 13 Apr 2005 12:31:43 -0700, Clay wrote:> > James Cotton wrote: >> I am designing a board with a TMS320F2811 chip, and have the > schematic >> done. I was about to start the layout but I wanted to ask if it can > work >> to make a double layered board (i saw a similar thread a while back, > but >> it didn't seem to answer this directly). I am only going to be using > the >> SCI pins and the analog inputs, so routing should be feasible. I was >> thinking about laying a ground plane under the chip and then a core > supply >> ring around that and a IO supply around that (C shapes, not complete >> circle) on the bottom layer, then decoupling capacitors on the bottom > too >> right below their respective pins. Is this feasible (college > student, >> just trying to save a buck on PCB manufacturing). >> >> Thank you, >> James > > Hello James, > This is a question with a not so simple answer. Certianly you have the > number of signals quite low, so routing them is not a real issue. But > you have started thinking about the real problem. Namely can you get > the power into the chip quietly. Most modern cpus have multiple power > pins where each pin powers a different portion of the chip. So > sometimes when you have improper decoupling, some functions in the chip > work while others act "dodgy." > > You "c" rings just may work - just pour as much copper as you can and > provide multiple decoupling caps. However any high speed design I would > do would have at least 4 layers. > > Do you really need a custom board, or can you get an eval board and add > on your stuff - either in a breadboard region or as a daughter board? > > IHTH, > Clay
Reply by ●April 15, 20052005-04-15
James Cotton wrote:> I probably could start w/ an eval board, but this is being designed for an > EEG system so needs to be isolated well. If I were to use an eval board I > would have either have to build a board w/ a bunch of isolation amplifier > (expensive part count) or an isolated ADC which would probably be fairly > easy. However, half the fun is the design and layout and eventually I'll > want to make my own version anyway, so I figured I might as well start > that way - esp. w/ the low signal count. It will probably be working at > fairly high frequencies to preprocess as much as possible b4 sending it to > the computer. If I got enough caps underneath the thing would my chances > be decent or am I more likely to get dodgy than not? > > Also, w/ regards to decoupling, I notice most of the schematics online for > the eval boards show many caps of a handful of values - I know this is to > get best filtering at various frequencies, but what is the optimal > placement plan. One cap per pin, regardless of value, and try and space > them out? One of each value at a couple of local star supplies? Even > distributed between a power ring and large ground pour w/ the pins making > connections to the power ring wherever convenient?Why not use an isolated power supply for the board? There are some available in brick form, and an isolation transformer between the power line and any other power supply works as well. For the power you are likely to need, a bank of alkaline D cells may be the most economical solution. Hospitals don't allow patients to use line-powered electric shavers -- my beard <http://users.erols.com/jyavins/me2.jpg> is a relic of such a prohibition -- but battery-powered shavers are allowed. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Reply by ●April 16, 20052005-04-16
> Why not use an isolated power supply for the board? There are some > available in brick form, and an isolation transformer between the power > line and any other power supply works as well. For the power you are > likely to need, a bank of alkaline D cells may be the most economical > solution. Hospitals don't allow patients to use line-powered electric > shavers -- my beard <http://users.erols.com/jyavins/me2.jpg> is a relic > of such a prohibition -- but battery-powered shavers are allowed. > > JerryI probably could, but as I said I'd want to design it at some point sanyway, and as much as anything - i want to design a dsp circuit. is it so challenging that i am destined for failure? I'm just curious if people get them to work as double layered designs, or if it is just so tight doing that it's not worth the work. James
Reply by ●April 18, 20052005-04-18
James Cotton <peabody124@gmail.com> wrote in news:pan.2005.04.15.01.25.34.239178@gmail.com:> I probably could start w/ an eval board, but this is being designed > for an EEG system so needs to be isolated well. If I were to use an > eval board I would have either have to build a board w/ a bunch of > isolation amplifier (expensive part count) or an isolated ADC which > would probably be fairly easy. However, half the fun is the design > and layout and eventually I'll want to make my own version anyway, so > I figured I might as well start that way - esp. w/ the low signal > count. It will probably be working at fairly high frequencies to > preprocess as much as possible b4 sending it to the computer. If I > got enough caps underneath the thing would my chances be decent or am > I more likely to get dodgy than not? > > Also, w/ regards to decoupling, I notice most of the schematics online > for the eval boards show many caps of a handful of values - I know > this is to get best filtering at various frequencies, but what is the > optimal placement plan. One cap per pin, regardless of value, and try > and space them out? One of each value at a couple of local star > supplies? Even distributed between a power ring and large ground pour > w/ the pins making connections to the power ring wherever convenient? > > Thanks, > James > > On Wed, 13 Apr 2005 12:31:43 -0700, Clay wrote: > >> >> James Cotton wrote: >>> I am designing a board with a TMS320F2811 chip, and have the >> schematic >>> done. I was about to start the layout but I wanted to ask if it can >> work >>> to make a double layered board (i saw a similar thread a while back, >> but >>> it didn't seem to answer this directly). I am only going to be >>> using >> the >>> SCI pins and the analog inputs, so routing should be feasible. I >>> was thinking about laying a ground plane under the chip and then a >>> core >> supply >>> ring around that and a IO supply around that (C shapes, not complete >>> circle) on the bottom layer, then decoupling capacitors on the >>> bottom >> too >>> right below their respective pins. Is this feasible (college >> student, >>> just trying to save a buck on PCB manufacturing). >>> >>> Thank you, >>> James >> >> Hello James, >> This is a question with a not so simple answer. Certianly you have >> the number of signals quite low, so routing them is not a real issue. >> But you have started thinking about the real problem. Namely can you >> get the power into the chip quietly. Most modern cpus have multiple >> power pins where each pin powers a different portion of the chip. So >> sometimes when you have improper decoupling, some functions in the >> chip work while others act "dodgy." >> >> You "c" rings just may work - just pour as much copper as you can and >> provide multiple decoupling caps. However any high speed design I >> would do would have at least 4 layers. >> >> Do you really need a custom board, or can you get an eval board and >> add on your stuff - either in a breadboard region or as a daughter >> board? >> >> IHTH, >> Clay >James, I think you are going to get into trouble with a two layer pcb. You should use 4 layers. I would use 1 layer for ground and 1 for power. If there is a core voltage lower than 3.3V, I would pour that layer under the part. Often this can be the same layer as the I/O supply (3.3V). If your part uses an internal PLL for clock multiplication, you must have a very good layout. Two layers will be probably be a disaster. I use 10nF caps for most of my decoupling (0805 or 0603 SMT). Do not use leaded parts for this. I try to layout the caps around the IC so that the positive connection is close to the power pins. Make sure the ground returns go directly tho the ground plane. I also usually use a few .1uF caps for each supply. The thing to remember is there is no such thing as a capacitor. There are only devices that approximate capacitors. This is why we use different values for decoupling. Our boards separate the DSP engine from the I/O functions (two boards). You might take a look at our special promo package. This is a system based on an Analog Devices SHARC and an Altera FPGA for only $200. It comes with a built in debugger and is supported by Visual DSP. The boards work like an EZ-Kit with more flexibility. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.com
Reply by ●April 19, 20052005-04-19
James, I have multiple boards with TMS320LF2406 (100pin), 2403 (64pin), 2402 (64pin), that have only two layers and they work just fine. I use ADC, JTAG, SPI ,CAP, EVM (PWM1-6). Also on these boards there are 6 power MOSFETs very close to DSP. Basicly it is a BLDC controller done on 4cm * 10cm board. Power and ground connections took some time to route. You will have some more work to do since you need 3.3V and 1.8V supply voltages. Good luck with routing Mitja
Reply by ●April 19, 20052005-04-19
"Korenje" <korenje@yahoo.co.uk> wrote in news:1113893925.156488.203920 @z14g2000cwz.googlegroups.com:> James, > > I have multiple boards with TMS320LF2406 (100pin), 2403 (64pin), 2402 > (64pin), that have only two layers and they work just fine. I use ADC, > JTAG, SPI ,CAP, EVM (PWM1-6). Also on these boards there are 6 power > MOSFETs very close to DSP. Basicly it is a BLDC controller done on 4cm > * 10cm board. Power and ground connections took some time to route. You > will have some more work to do since you need 3.3V and 1.8V supply > voltages. > > Good luck with routing > > Mitja > >I once built a two layer board with an ADI ADSP-2191. This DSP ran at about 150MHz with an input clock of 25MHz. I poured the 2.5V core carefully under the part since the core voltage supplies thge high speed stuff. I then routed the 3.3V I/O with fat traces with good ground returns. The board did not have a lot of peripherals and nothing external was fast. I poured a ground plane on the top and bottom sides of the board. I didn't skimp on decoupling capacitors, etc. Results: The board worked fine until I wanted to use the internal PLL. The PLL ran off 3.3V instead of the core. The board also failed some EMC tests for susceptability. I modified the board by just adding a 3.3V power plane and a ground plane. The board worked great!. This was the last two layer board I ever used for a DSP. I'm not saying its impossible to use two layers, I'm suggesting that the probability of success is much less than 100%. There are many pcb houses that will produce multilayer pcbs for relatively low cost in prototype quantities. Its much more expensive to get it wrong the first time. I started my engineering career as an analog guy, so I generally pay lots of attention to layout. Careful routing is important in all cases. You can't just connect the dots. I rarely use an autorouter because the router makes way too many bad decisions. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.com
Reply by ●April 20, 20052005-04-20
> The board worked fine until I wanted to use the internal PLL. The PLL ran > off 3.3V instead of the core. The board also failed some EMC tests for > susceptability.Thank you pretty much convinced me since that is a pretty similar setup to mine with the PLL usage and such. 4 it is :)> I started my engineering career as an analog guy, so I generally pay lots > of attention to layout. Careful routing is important in all cases. You > can't just connect the dots. I rarely use an autorouter because the > router makes way too many bad decisions.Amen. It takes longer too since you spend so long trying to underdo it's stupidity. Thanks again, James
Reply by ●April 22, 20052005-04-22
James Cotton <peabody124@gmail.com> wrote in news:pan.2005.04.15.01.25.34.239178@gmail.com:> I probably could start w/ an eval board, but this is being designed > for an EEG system so needs to be isolated well. If I were to use an > eval board I would have either have to build a board w/ a bunch of > isolation amplifier (expensive part count) or an isolated ADC which > would probably be fairly easy. However, half the fun is the design > and layout and eventually I'll want to make my own version anyway, so > I figured I might as well start that way - esp. w/ the low signal > count. It will probably be working at fairly high frequencies to > preprocess as much as possible b4 sending it to the computer. If I > got enough caps underneath the thing would my chances be decent or am > I more likely to get dodgy than not? > > Also, w/ regards to decoupling, I notice most of the schematics online > for the eval boards show many caps of a handful of values - I know > this is to get best filtering at various frequencies, but what is the > optimal placement plan. One cap per pin, regardless of value, and try > and space them out? One of each value at a couple of local star > supplies? Even distributed between a power ring and large ground pour > w/ the pins making connections to the power ring wherever convenient? > > Thanks, > James > > On Wed, 13 Apr 2005 12:31:43 -0700, Clay wrote: > >> >> James Cotton wrote: >>> I am designing a board with a TMS320F2811 chip, and have the >> schematic >>> done. I was about to start the layout but I wanted to ask if it can >> work >>> to make a double layered board (i saw a similar thread a while back, >> but >>> it didn't seem to answer this directly). I am only going to be >>> using >> the >>> SCI pins and the analog inputs, so routing should be feasible. I >>> was thinking about laying a ground plane under the chip and then a >>> core >> supply >>> ring around that and a IO supply around that (C shapes, not complete >>> circle) on the bottom layer, then decoupling capacitors on the >>> bottom >> too >>> right below their respective pins. Is this feasible (college >> student, >>> just trying to save a buck on PCB manufacturing). >>> >>> Thank you, >>> James >> >> Hello James, >> This is a question with a not so simple answer. Certianly you have >> the number of signals quite low, so routing them is not a real issue. >> But you have started thinking about the real problem. Namely can you >> get the power into the chip quietly. Most modern cpus have multiple >> power pins where each pin powers a different portion of the chip. So >> sometimes when you have improper decoupling, some functions in the >> chip work while others act "dodgy." >> >> You "c" rings just may work - just pour as much copper as you can and >> provide multiple decoupling caps. However any high speed design I >> would do would have at least 4 layers. >> >> Do you really need a custom board, or can you get an eval board and >> add on your stuff - either in a breadboard region or as a daughter >> board? >> >> IHTH, >> Clay >James, I think you are going to get into trouble with a two layer pcb. You should use 4 layers. I would use 1 layer for ground and 1 for power. If there is a core voltage lower than 3.3V, I would pour that layer under the part. Often this can be the same layer as the I/O supply (3.3V). If your part uses an internal PLL for clock multiplication, you must have a very good layout. Two layers will be probably be a disaster. I use 10nF caps for most of my decoupling (0805 or 0603 SMT). Do not use leaded parts for this. I try to layout the caps around the IC so that the positive connection is close to the power pins. Make sure the ground returns go directly tho the ground plane. I also usually use a few .1uF caps for each supply. The thing to remember is there is no such thing as a capacitor. There are only devices that approximate capacitors. This is why we use different values for decoupling. Our boards separate the DSP engine from the I/O functions (two boards). You might take a look at our special promo package. This is a system based on an Analog Devices SHARC and an Altera FPGA for only $200. It comes with a built in debugger and is supported by Visual DSP. The boards work like an EZ-Kit with more flexibility. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.com
