Signal mixing on a delta-sigma ADC

Started by Piotr Wyderski June 21, 2017
I have a delta-sigma ADC with exposed modulator input pin.
Its definition is as follows:

"Modulator Input is used to dynamically control the polarity
of the signal in the modulator. Polarity is inverted when
“mi” input is high. This input signal allows the user to modulate
the input signal with an independent clock to act as a signal mixer."

OK, I can see what happens if the modulator input frequency is
much lower than the effencive sampling frequency of the ADC.
But what in the case of undersampling? Say, the effective
sampling frequency is 10kHz, the signal bandwidth is 3kHz
centered at 100kHz, the mixer input is also changing at 100kHz
to produce a homodyne. The ADC is capable of 384kSPS, so its
S/H stage will have no problems with mere 100kHz. But what would
be the meaning of the ADC output values?

	Best regards, Piotr
I suspect that the ADC is a continuous-time delta-sigma type with a differential
input. The modulator input pin is probably just swapping the differential inputs at
the virtual ground of the input op-amp. If the modulator is a continuous-time design
then there is no input S+H. In this case the system just multiplies the input by the
+/-1 stream that is applied at the modulator pin, and then this is converted by the
delta sigma adc. Most continuous-time modulators have an inherent anti-alias
property so you don't need to worry about aliasing. 
If on the other hand the ADC design is using switched-cap design techniques, then
the situation is more complicated. 

Bob
radams2000@gmail.com wrote:

> I suspect that the ADC is a continuous-time delta-sigma type with a differential
input. It is exactly the delta-sigma present in the PSOC5LP line: http://www.cypress.com/file/128166/download Yes, I plan to use it in differential mode.
> The modulator input pin is probably just swapping the differential inputs at the
virtual ground of the input op-amp. > If the modulator is a continuous-time design then there is no input S+H. That would explain the lack of the "end of sampling" output, which is present in the two remaining SAR ADCs. Thank you for your remarks!
> Most continuous-time modulators have an inherent anti-alias property so you don't
need to worry about aliasing.
> If on the other hand the ADC design is using switched-cap design techniques, then
the situation is more complicated. I am unable to find it in the documentation. "The PSoC 5LP Delta Sigma converter has a third-order modulator, followed by a fourth-order decimation filter. The modulator has a high impedance front end buffer followed by a bypassable RC filter." That's pretty all they say. Best regards, Piotr