DSM integrator - how many bits?

Started by Piotr Wyderski August 12, 2017
I'd like to implement a first-order delta-sigma power
amplifier in Verilog. The input stream is N=16-bit wide
(signed). How many bits should the integrator have?
Common sense says it would be enough for the worst-case
delta (=N+1) + the actual content (also N+1), so N+2 bits.
Is it correct? Can it be done with just N?

	Best regards, Piotr
On Sat, 12 Aug 2017 17:26:20 +0200, Piotr Wyderski wrote:

> I'd like to implement a first-order delta-sigma power amplifier in > Verilog. The input stream is N=16-bit wide (signed). How many bits > should the integrator have? Common sense says it would be enough for the > worst-case delta (=N+1) + the actual content (also N+1), so N+2 bits. > Is it correct? Can it be done with just N?
That depends entirely on the specifications you have to meet. Unless you're clocking it at roughly 2^16 times the passband of the output filter, you're not going to be using your full 16 bits of input precision. You really need to do some analysis, backed up with simulation. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Tim Wescott wrote:

> That depends entirely on the specifications you have to meet.
An audio amp for emergency messages, no HiFi requirements. Since the data at all the stages is digital, I thought it would be neat not to go through a DAC and a linear amplifier, but make the analog signal materialize at the speaker. A first order delta-sigma D class amplifier made of an abused dual low-side MOSFET driver MIC4427 + some Verilog. Just for fun, I have a spare current DAC as a fallback.
> Unless you're clocking it at roughly 2^16 times the passband of the output > filter, you're not going to be using your full 16 bits of input precision.
Yes, the more I experiment with delta-sigma, the more cheating it appears to be.
> You really need to do some analysis, backed up with simulation.
And N+2 seems to be the limit. Thanks, Tim! Best regaards, Piotr