Hi Randy, W dniu 25.02.2018 o 13:18, Randy Yates pisze: (...)>> You are right. If the input signal to either of the ADCs has a bandwidth >> greater than Fs / 2, where Fs = 1 MHz, then you will have aliasing and >> that will be bad/unrecoverable.you are wrong. Sample stream from one ADC will have aliasing, but we have interleaved stream from TWO ADC, at proper time distance between samples. The signal amplitude measurement METHOD has no meaning from sampling theorem point of view. Think of pipeline ADC: there n-samples are processed simultaneously. And think of ADC back box, then the operation you mentioned is just decimation by 2, so then we have to use DIGITAL decimation filter, and we can take even or odd samples streams. Interleaved stream of samples from both ADCs have a full info about input signal. Kind regards Roman Rumian

# Multiple ADCs and aliasing

Started by ●February 23, 2018

Reply by ●February 25, 20182018-02-25

Reply by ●February 25, 20182018-02-25

rr <rr@somwhere.com> writes:> Hi Randy, > > W dniu 25.02.2018 o 13:18, Randy Yates pisze: > (...) >>> You are right. If the input signal to either of the ADCs has a bandwidth >>> greater than Fs / 2, where Fs = 1 MHz, then you will have aliasing and >>> that will be bad/unrecoverable. > > you are wrong. > Sample stream from one ADC will have aliasing, but we have interleaved > stream from TWO ADC, at proper time distance between samples. > > The signal amplitude measurement METHOD has no meaning from sampling > theorem point of view. > > Think of pipeline ADC: there n-samples are processed simultaneously. > > And think of ADC back box, then the operation you mentioned is just > decimation by 2, so then we have to use DIGITAL decimation filter, and > we can take even or odd samples streams. > > Interleaved stream of samples from both ADCs have a full info about > input signal. > > Kind regards > > Roman RumianHi Roman, Let me ask you for clarification: are you saying that if x(t) is an input signal with a 1 MHz bandwidth, and x(t) is applied to a single, "real" ADC sampling at 1 MHz, you will not get aliasing? If so, please explain why not. Or are you saying that you will get aliasing but it will somehow not matter when you combine it with the second ADC? Since aliasing is non-linear, I'm not sure how this could possibly be done. -- Randy Yates, DSP/Embedded Firmware Developer Digital Signal Labs http://www.digitalsignallabs.com

Reply by ●February 25, 20182018-02-25

W dniu 25.02.2018 o 18:37, Randy Yates pisze: (...) > > Hi Roman, > > Let me ask you for clarification: are you saying that if x(t) is an > input signal with a 1 MHz bandwidth, and x(t) is applied to a single, > "real" ADC sampling at 1 MHz, you will not get aliasing? > > If so, please explain why not. > > Or are you saying that you will get aliasing but it will somehow not > matter when you combine it with the second ADC? Since aliasing is > non-linear, I'm not sure how this could possibly be done. > No, Piotr question is about TWO 1 Msps ADCs converting 1 MHz bandwith signal in two phase, interleave mode: "... I have two 1MHz ADCs and would like to interleave them by a half of the sampling cycle in order to get a single ADC with effective sampling frequency of 2MHz ... " Regards, Roman Rumian

Reply by ●February 25, 20182018-02-25

W dniu 2018-02-25 o 22:09, rr pisze: (...)> No, Piotr question is about TWO 1 Msps ADCs converting 1 MHz bandwith > signal in two phase, interleave mode: > "... > I have two 1MHz ADCs and would like to interleave them > by a half of the sampling cycle in order to get a single > ADC with effective sampling frequency of 2MHz ... "Here: http://www.ti.com/product/adc12dj3200 is an example of chip implementing such a method. Sample and Hold circuits of both ADCs have a very high BW(much higher then Fs/2), and in single channel mode two 3.2 Gsps ADCs (and its S/H circuits) work in two phase interleaved mode. Regards, Roman Rumian

Reply by ●February 25, 20182018-02-25

On Sunday, February 25, 2018 at 9:37:40 AM UTC-8, Randy Yates wrote:> ...> Hi Roman, > > Let me ask you for clarification: are you saying that if x(t) is an > input signal with a 1 MHz bandwidth, and x(t) is applied to a single, > "real" ADC sampling at 1 MHz, you will not get aliasing? > > If so, please explain why not. > > Or are you saying that you will get aliasing but it will somehow not > matter when you combine it with the second ADC? Since aliasing is > non-linear, I'm not sure how this could possibly be done. > -- > Randy Yates, DSP/Embedded Firmware DeveloperRandy Look at it another way. If you have a < 1 MHz (but almost 1 MHz) BW signal sampled at 2 MHz and you only look at the even or the odd samples, you will have a 1MHz sample rate with aliasing. What about your "non-linearity of aliasing" keeps you from reinterleaving the even and odd samples and having the alias free 2 MHz sample set again? Dale B. Dalrymple

Reply by ●February 25, 20182018-02-25

dbd <d.dalrymple@sbcglobal.net> writes:> On Sunday, February 25, 2018 at 9:37:40 AM UTC-8, Randy Yates wrote: >> ... > >> Hi Roman, >> >> Let me ask you for clarification: are you saying that if x(t) is an >> input signal with a 1 MHz bandwidth, and x(t) is applied to a single, >> "real" ADC sampling at 1 MHz, you will not get aliasing? >> >> If so, please explain why not. >> >> Or are you saying that you will get aliasing but it will somehow not >> matter when you combine it with the second ADC? Since aliasing is >> non-linear, I'm not sure how this could possibly be done. >> -- >> Randy Yates, DSP/Embedded Firmware Developer > > Randy > > Look at it another way. If you have a < 1 MHz (but almost 1 MHz) BW > signal sampled at 2 MHz and you only look at the even or the odd > samples, you will have a 1MHz sample rate with aliasing. What about > your "non-linearity of aliasing" keeps you from reinterleaving the > even and odd samples and having the alias free 2 MHz sample set again?Thanks Dale, that is very helpful. The remaining challenge for me is to show myself mathematically (ideally, theoretically) how this can happen. -- Randy Yates, DSP/Embedded Firmware Developer Digital Signal Labs http://www.digitalsignallabs.com

Reply by ●February 26, 20182018-02-26

Randy Yates <yates@digitalsignallabs.com> writes:> dbd <d.dalrymple@sbcglobal.net> writes: > >> On Sunday, February 25, 2018 at 9:37:40 AM UTC-8, Randy Yates wrote: >>> ... >> >>> Hi Roman, >>> >>> Let me ask you for clarification: are you saying that if x(t) is an >>> input signal with a 1 MHz bandwidth, and x(t) is applied to a single, >>> "real" ADC sampling at 1 MHz, you will not get aliasing? >>> >>> If so, please explain why not. >>> >>> Or are you saying that you will get aliasing but it will somehow not >>> matter when you combine it with the second ADC? Since aliasing is >>> non-linear, I'm not sure how this could possibly be done. >>> -- >>> Randy Yates, DSP/Embedded Firmware Developer >> >> Randy >> >> Look at it another way. If you have a < 1 MHz (but almost 1 MHz) BW >> signal sampled at 2 MHz and you only look at the even or the odd >> samples, you will have a 1MHz sample rate with aliasing. What about >> your "non-linearity of aliasing" keeps you from reinterleaving the >> even and odd samples and having the alias free 2 MHz sample set again? > > Thanks Dale, that is very helpful. The remaining challenge for me is to > show myself mathematically (ideally, theoretically) how this can happen.OK that wasn't too hard. I used the infinite impulse train model of sampling. I created an Fs-spaced, frequency domain impulse train, P1(w), and then created P2(w) from it using the Fourier transform property x(t - t0) = e^(-j * w * t0) * X(w), where t0 = Ts / 2. Therefore P2(w) = G(w) * P1(w), where G(w) = e^{-j * w * Ts). Then I noticed that G(n * Ws) = (-1)^n, Ws = 2 * pi * Fs Therefore P(w) = P1(w) + P2(w) which is a 2 * Fs impulse train. I guess the phallacy in my logic is that, once aliasing is introduced, it is impossible to remove. That has been driven into my mind for so long it took some effort to thwart. -- Randy Yates, DSP/Embedded Firmware Developer Digital Signal Labs http://www.digitalsignallabs.com

Reply by ●February 26, 20182018-02-26

Randy Yates <yates@digitalsignallabs.com> writes:> where G(w) = e^{-j * w * Ts).Correction: G(w) = e^{-j * w * Ts / 2}. -- Randy Yates, DSP/Embedded Firmware Developer Digital Signal Labs http://www.digitalsignallabs.com

Reply by ●February 26, 20182018-02-26

rr <rr@somwhere.com> writes:> W dniu 25.02.2018 o 18:37, Randy Yates pisze: > (...) >> >> Hi Roman, >> >> Let me ask you for clarification: are you saying that if x(t) is an >> input signal with a 1 MHz bandwidth, and x(t) is applied to a single, >> "real" ADC sampling at 1 MHz, you will not get aliasing? >> >> If so, please explain why not. >> >> Or are you saying that you will get aliasing but it will somehow not >> matter when you combine it with the second ADC? Since aliasing is >> non-linear, I'm not sure how this could possibly be done. >> > No, Piotr question is about TWO 1 Msps ADCs converting 1 MHz bandwith > signal in two phase, interleave mode: > "... > I have two 1MHz ADCs and would like to interleave them > by a half of the sampling cycle in order to get a single > ADC with effective sampling frequency of 2MHz ... "I am clear on Piotr's question. The point is, if you consider one of the two ADCs (either one) independent of the other, it will (in general) experience aliasing. This was actually part of Piotr's original question, and Piotr is correct on this point. -- Randy Yates, DSP/Embedded Firmware Developer Digital Signal Labs http://www.digitalsignallabs.com

Reply by ●February 27, 20182018-02-27

Hi Randy. Have you seen the "interleaved ADC" webinar at http://hosted.verticalresponse.com/1940905/876581eed7/544320746/1e257ed5fb/ [-Rick-]