Multiple ADCs and aliasing

Hi Randy.
Have you seen the "interleaved ADC" webinar at:

http://hosted.verticalresponse.com/1940905/876581eed7/544320746/1e257ed5fb/

[-Rick Lyons-]

Hi Randy,

W dniu 27.02.2018 o 03:47, Randy Yates pisze:
> rr <rr@somwhere.com> writes:
(...)
>> No, Piotr question is about TWO 1 Msps ADCs converting 1 MHz bandwith
>> signal in two phase, interleave mode:
>> "...
>> I have two 1MHz ADCs and would like to interleave them
>> by a half of the sampling cycle in order to get a single
>> ADC with effective sampling frequency of 2MHz ... "
> 
> I am clear on Piotr's question. The point is, if you consider one of the
> two ADCs (either one) independent of the other, it will (in general)
> experience aliasing. This was actually part of Piotr's original
> question, and Piotr is correct on this point.

yes, of course, if we sample 1 MHz bandwidth analog signal at 1 Msps 
rate, the sample stream will contain aliasing, but dependency has no 
meaning, because of too low sampling FREQUENCY, and single ADC is 
independent (making them dependent has no sense). Regular time intervals 
between samples counts only. Each of two sample streams from dependent 
ADCs experience aliasing, but not together.

Actually, the aliasing problem in Piotr case is solved by two 
synchronized S/H blocks, sampling at Fs/2 frequency BUT having analog 
input BW Fs/2 minimum, AND sampling clock jitter tuned to maximum 
frequency of input signal. Two S/H circuits must be used to give each of 
ADCs enough time (1us) for measurement (conversion).

In case of two millions such a S/H circuits there is the possibility to 
convert this signal by two million people equipped with voltmeters. ;-)

With regards,

Roman Rumian

r.lyons@ieee.org writes:

> Hi Randy. 
> Have you seen the "interleaved ADC" webinar at
> http://hosted.verticalresponse.com/1940905/876581eed7/544320746/1e257ed5fb/
>
> [-Rick-]

Hey Rick!

Not until now. I'll watch when I get a chance. Those guys look like
they would know what they're doing..
-- 
Randy Yates, Embedded Linux Developer
Garner Underground, Inc.
http://www.garnerundergroundinc.com

rr <rr@somwhere.com> writes:

> Hi Randy,
>
> W dniu 27.02.2018 o&nbsp;03:47, Randy Yates pisze:
>> rr <rr@somwhere.com> writes:
> (...)
>>> No, Piotr question is about TWO 1 Msps ADCs converting 1 MHz bandwith
>>> signal in two phase, interleave mode:
>>> "...
>>> I have two 1MHz ADCs and would like to interleave them
>>> by a half of the sampling cycle in order to get a single
>>> ADC with effective sampling frequency of 2MHz ... "
>>
>> I am clear on Piotr's question. The point is, if you consider one of the
>> two ADCs (either one) independent of the other, it will (in general)
>> experience aliasing. This was actually part of Piotr's original
>> question, and Piotr is correct on this point.
>
> yes, of course, if we sample 1 MHz bandwidth analog signal at 1 Msps
> rate, the sample stream will contain aliasing, but dependency has no
> meaning, because of too low sampling FREQUENCY, and single ADC is
> independent (making them dependent has no sense). Regular time
> intervals between samples counts only. Each of two sample streams from
> dependent ADCs experience aliasing, but not together.

Roman,

In my opinion you are overlooking the most relevent portion of 
Piotr's question, which was also the question I had in my mind.

All my life I've had it drilled it into my head, unconditionally, that
once aliasing occurs, it is irreversible. Until now I don't ever
remember anyone teaching me, "Aliasing can be reversed in certain
cases."

Contributing (in my opinion) to the confusion in this thread is that
some of the answers (including yours, and including the Analog Devices
article that was cited) mix theoretical with practical considerations.
Again, I think Piotr's first and foremost question was, "How can
aliasing in an ADC ever be undone?" The answer to that question is
purely theoretical and has absolutely nothing to do with practical
considerations.

Further contributing (in my opinion) to the confusion in this thread is
that nowhere (until my answer describing the modulation model of
sampling) was a clear theoretical explanation provided.

I'm not saying practical considerations aren't important. I'm just
saying I don't think they answer Piotr's most fundamental question, and
I know they didn't answer mine.

In any case, I appreciate the discussion. I learned something here and
that is very valuable.
-- 
Randy Yates, Embedded Linux Developer
Garner Underground, Inc.
http://www.garnerundergroundinc.com

On 27.2.18 17:48, Randy Yates wrote:
> rr <rr@somwhere.com> writes:
> 
>> Hi Randy,
>>
>> W dniu 27.02.2018 o&nbsp;03:47, Randy Yates pisze:
>>> rr <rr@somwhere.com> writes:
>> (...)
>>>> No, Piotr question is about TWO 1 Msps ADCs converting 1 MHz bandwith
>>>> signal in two phase, interleave mode:
>>>> "...
>>>> I have two 1MHz ADCs and would like to interleave them
>>>> by a half of the sampling cycle in order to get a single
>>>> ADC with effective sampling frequency of 2MHz ... "
>>>
>>> I am clear on Piotr's question. The point is, if you consider one of the
>>> two ADCs (either one) independent of the other, it will (in general)
>>> experience aliasing. This was actually part of Piotr's original
>>> question, and Piotr is correct on this point.
>>
>> yes, of course, if we sample 1 MHz bandwidth analog signal at 1 Msps
>> rate, the sample stream will contain aliasing, but dependency has no
>> meaning, because of too low sampling FREQUENCY, and single ADC is
>> independent (making them dependent has no sense). Regular time
>> intervals between samples counts only. Each of two sample streams from
>> dependent ADCs experience aliasing, but not together.
> 
> Roman,
> 
> In my opinion you are overlooking the most relevent portion of
> Piotr's question, which was also the question I had in my mind.
> 
> All my life I've had it drilled it into my head, unconditionally, that
> once aliasing occurs, it is irreversible. Until now I don't ever
> remember anyone teaching me, "Aliasing can be reversed in certain
> cases."
> 
> Contributing (in my opinion) to the confusion in this thread is that
> some of the answers (including yours, and including the Analog Devices
> article that was cited) mix theoretical with practical considerations.
> Again, I think Piotr's first and foremost question was, "How can
> aliasing in an ADC ever be undone?" The answer to that question is
> purely theoretical and has absolutely nothing to do with practical
> considerations.
> 
> Further contributing (in my opinion) to the confusion in this thread is
> that nowhere (until my answer describing the modulation model of
> sampling) was a clear theoretical explanation provided.
> 
> I'm not saying practical considerations aren't important. I'm just
> saying I don't think they answer Piotr's most fundamental question, and
> I know they didn't answer mine.
> 
> In any case, I appreciate the discussion. I learned something here and
> that is very valuable.


If the ADC samplings are properly staggered and the resulting
number stream interleaved, how does the result differ from one
sampled at twice the original rate?

-- 

-TV

Hi Randy,

W dniu 27.02.2018 o 16:48, Randy Yates pisze:
(...)
> Roman,
> 
> In my opinion you are overlooking the most relevent portion of
> Piotr's question, which was also the question I had in my mind.

So, let's look at this question again:
"...But the aliasing properties of the data stream will be as if the
signal was sampled at 1MHz because the ADCs are independent
blocks and don't influence each other, right? "

My answer to his question is: no,
because Piotr overlooked what he assumed:
"I have two 1MHz ADCs and would like to interleave them
by a half of the sampling cycle in order to get a single
ADC with effective sampling frequency of 2MHz ..."

This means, that he thinks about using exactly the same sampling 
frequency (1MHz; not one 1MHz and second 1.0000000001 Mhz or anything 
else different from 1 MHz; hm, well, this may also mean that 1MHz is 
just one of ADC chip parameters ...), and they will be interleaved by 
half of the sampling cycle (it is possible with the same sampling clock 
ONLY), so, the obvious conclusion is that ADCs work SYNCHRONOUSLY, in 
STRONGLY DEPENDENT manner.

> All my life I've had it drilled it into my head, unconditionally, that
> once aliasing occurs, it is irreversible. Until now I don't ever
> remember anyone teaching me, "Aliasing can be reversed in certain
> cases."

Yes, that is true, but we have no aliasing in combined, interleaved 
sample stream. :-)

You have probably overlooked, that we can reverse this point of view to 
situation, where correctly sampled signal can be seen as two DEPENDENT 
streams od even and odd samples.
What could we say about them and aliasing ?

> Contributing (in my opinion) to the confusion in this thread is that
> some of the answers (including yours, and including the Analog Devices
> article that was cited) mix theoretical with practical considerations.
> Again, I think Piotr's first and foremost question was, "How can
> aliasing in an ADC ever be undone?" The answer to that question is
> purely theoretical and has absolutely nothing to do with practical
> considerations.

My answer is: aliasing can be undone by replenishment of missing samples 
provided by the second ADC (working in synchronous, interleaved way).

Hm, this is very practical consideration for me and probably for Piotr, 
and also for companies manufacturing chips like mentioned ADC12DJ3200, 
but can understand that for you this is absolutely theoretical, 
interesting question.

Thank you,

Roman

Tauno Voipio <tauno.voipio@notused.fi.invalid> writes:

> On 27.2.18 17:48, Randy Yates wrote:
>> rr <rr@somwhere.com> writes:
>>
>>> Hi Randy,
>>>
>>> W dniu 27.02.2018 o&nbsp;03:47, Randy Yates pisze:
>>>> rr <rr@somwhere.com> writes:
>>> (...)
>>>>> No, Piotr question is about TWO 1 Msps ADCs converting 1 MHz bandwith
>>>>> signal in two phase, interleave mode:
>>>>> "...
>>>>> I have two 1MHz ADCs and would like to interleave them
>>>>> by a half of the sampling cycle in order to get a single
>>>>> ADC with effective sampling frequency of 2MHz ... "
>>>>
>>>> I am clear on Piotr's question. The point is, if you consider one of the
>>>> two ADCs (either one) independent of the other, it will (in general)
>>>> experience aliasing. This was actually part of Piotr's original
>>>> question, and Piotr is correct on this point.
>>>
>>> yes, of course, if we sample 1 MHz bandwidth analog signal at 1 Msps
>>> rate, the sample stream will contain aliasing, but dependency has no
>>> meaning, because of too low sampling FREQUENCY, and single ADC is
>>> independent (making them dependent has no sense). Regular time
>>> intervals between samples counts only. Each of two sample streams from
>>> dependent ADCs experience aliasing, but not together.
>>
>> Roman,
>>
>> In my opinion you are overlooking the most relevent portion of
>> Piotr's question, which was also the question I had in my mind.
>>
>> All my life I've had it drilled it into my head, unconditionally, that
>> once aliasing occurs, it is irreversible. Until now I don't ever
>> remember anyone teaching me, "Aliasing can be reversed in certain
>> cases."
>>
>> Contributing (in my opinion) to the confusion in this thread is that
>> some of the answers (including yours, and including the Analog Devices
>> article that was cited) mix theoretical with practical considerations.
>> Again, I think Piotr's first and foremost question was, "How can
>> aliasing in an ADC ever be undone?" The answer to that question is
>> purely theoretical and has absolutely nothing to do with practical
>> considerations.
>>
>> Further contributing (in my opinion) to the confusion in this thread is
>> that nowhere (until my answer describing the modulation model of
>> sampling) was a clear theoretical explanation provided.
>>
>> I'm not saying practical considerations aren't important. I'm just
>> saying I don't think they answer Piotr's most fundamental question, and
>> I know they didn't answer mine.
>>
>> In any case, I appreciate the discussion. I learned something here and
>> that is very valuable.
>
>
> If the ADC samplings are properly staggered and the resulting
> number stream interleaved, how does the result differ from one
> sampled at twice the original rate?

It does not differ. The question in my mind was, why didn't the aliasing
in the individual converters screw things up? Until you can prove
analytically how this aliasing is "undone", you're waving your hands, no
matter how intuitive it may seem from other points-of-view. Intuition is
not proof! If it is true, it should be provable.

Analogy: Did Shannon/Nyquist merely assert that the input bandwidth to a
single, real (time) quantizer running at a rate of Fs quantizations per
second must be less than Fs / 2? Or did they prove why it must be so?!?

All the responses I've seen so far have been faith-based.
-- 
Randy Yates, Embedded Linux Developer
Garner Underground, Inc.
http://www.garnerundergroundinc.com

rr <rr@somwhere.com> writes:
> [...]
> Yes, that is true, but we have no aliasing in combined, interleaved
> sample stream. :-)

That is an assertion, not a proof. For all the time you've spent
discussing this, you could have easily come up with the proof. It took
me about a half an hour.
-- 
Randy Yates, Embedded Linux Developer
Garner Underground, Inc.
http://www.garnerundergroundinc.com

Randy Yates  <randyy@garnerundergroundinc.com> wrote:

>In my opinion you are overlooking the most relevent portion of 

>
>All my life I've had it drilled it into my head, unconditionally, that
>once aliasing occurs, it is irreversible. Until now I don't ever
>remember anyone teaching me, "Aliasing can be reversed in certain
>cases." [..]
>Further contributing (in my opinion) to the confusion in this thread is
>that nowhere (until my answer describing the modulation model of
>sampling) was a clear theoretical explanation provided.

Aliasing occurs when sampling.  This signal is being sampled at 2 Ms/sec.

You can take a sampled signal (2 Ms/sec in this case) and sub-sample it
(into two 1 Ms/sec signals), and those individual sub-sampled signals certainly 
exhibit additional aliasing.  But the total signal, sampled at 2 Ms/sec, does 
not exhibit this additional aliasing.

How this sampled signal is formatted and presented to the next layer of the
system has no theoretical aspects, so there is no such thing as a further theoretical
explanation for the lack of additional aliasing... you get the aliasing that
is associated with the sampling you have performed.  If you throw out one of the
two streams in this case, you get additional aliasing; if you keep them both, you 
do not.

Steve

spope384@gmail.com (Steve Pope) writes:

> Randy Yates  <randyy@garnerundergroundinc.com> wrote:
>
>>In my opinion you are overlooking the most relevent portion of 
>
>>
>>All my life I've had it drilled it into my head, unconditionally, that
>>once aliasing occurs, it is irreversible. Until now I don't ever
>>remember anyone teaching me, "Aliasing can be reversed in certain
>>cases." [..]
>>Further contributing (in my opinion) to the confusion in this thread is
>>that nowhere (until my answer describing the modulation model of
>>sampling) was a clear theoretical explanation provided.
>
> Aliasing occurs when sampling.  This signal is being sampled at 2
> Ms/sec.

Steve,

That is an unproven assertion. The standard treatment of sampling theory
involves the use of a SINGLE quantizer sampling at Fs samples per second
with Fs/2 bandwidth. It almost always involves the use of a (single)
infinite impulse train, modulating the input signal with that, etc.

Creating an alternate sampling architecture which uses two quantizers
and claiming it is equivalent to sampling at twice the sample rate
requires a theoretical basis to establish its validity. Otherwise it's
just an assertion.
-- 
Randy Yates, Embedded Linux Developer
Garner Underground, Inc.
http://www.garnerundergroundinc.com