Does decimating after Sampling mean loss of data?

Started by Mehtap özkan June 27, 2018
Dear All,
I use an AD9371 board and on it the ADC samples the input at 1228 MHz, then the
sampled data is decimated by 5 and a downsampling FIR filter reduces the output rate
to 122.8 MSPS. This is what I have as an input to the FPGA where demodulation
occurs.
 The signal to be demodulated is an 80 MHz wide QPSK modulated one. For ideal
demodulation I need a 320 MSPS (x4 symbol rate).
 My question is: 
Can I use a rational resampler to get 320 MSPS from the 122.8 MSPS input or are the
decimated and filtered samples worth only 122.8 MSPS and I have to live with it.
 So is decimated and filtered data lost forever?
Thanks in advance. 
Mehtap &ouml;zkan  <kurtulmehtap@gmail.com> wrote:

>Dear All, >I use an AD9371 board and on it the ADC samples the input at 1228 MHz, >then the sampled data is decimated by 5 and a downsampling FIR filter >reduces the output rate to 122.8 MSPS. This is what I have as an input >to the FPGA where demodulation occurs. > The signal to be demodulated is an 80 MHz wide QPSK modulated one. For >ideal demodulation I need a 320 MSPS (x4 symbol rate). > My question is: >Can I use a rational resampler to get 320 MSPS from the 122.8 MSPS input >or are the decimated and filtered samples worth only 122.8 MSPS and I >have to live with it. > So is decimated and filtered data lost forever?
Potentially, yes. It depends on your signal. If there is noise or interference and the decimation causes these unwanted signal components to alias into you 80 MHz passband, then you have lost signal quality. If it's a clean signal coming in, then you will be okay. Steve