Hi, we are reading an ADC o/p through FPGA. To remove the DC Offset present in the ADC input we have a DAC which can remove this DC offset using a subtractor before the actual analog input (with added DC offset) goes to ADC. Now I want my FPGA to calculate the DC offset from ADC outputs and then feed this value to DAC input which in turn cancel the DC offset using subtrator. can anybody suggest me how can i implement this in FPGA? I just gone through net and realized that i can use a subtractor and a MAC. The ADC output will go to this Subtractor which has the final output of MAC as other input. the subtractor output will be multiplied with some small value K (??) and then an accumulator. The final output of accumulator can be feedback to the DAC. The DAC o/p is going to Mixer to cancel the DC offset? this is what i understood. can somebody through some light? suggestions are welcome.
DC offset removal through FPGA
Started by ●June 23, 2005
Reply by ●June 23, 20052005-06-23
Reply by ●June 23, 20052005-06-23
shridhar wrote:> Now I want my FPGA to calculate the DC offset from ADC outputs and then > feed this value to DAC input which in turn cancel the DC offset using > subtrator....> suggestions are welcome.http://www.dspguru.com/comp.dsp/tricks/alg/dc_block.htm Regards, Andor
Reply by ●June 23, 20052005-06-23
shridhar@mistralsoftware.com wrote:> Hi,One trick you could try would be to perform your accumulation over a power of two number of samples (e.g. 64, 128, etc). This would obviate the need for multiplication since division by powers of two can be accomplished by bit shifting to the right. Without having to use a barrel shifter, you could for instance align the read latch for your subtraction register such that it's lsb is aligned with the Kth bit of the accumulator. For example,if you wanted to remove the running average of 64 samples you simply align the latch with bit 7 (assuming bit zero is the LSB) of your accumulator thus discarding the lower 6 bits. Be careful, for instance if you are using a bipolar ADC, that you do not neglect to implement the correct sign extension logic and two's complement arithmetic. That said, you can work wonders with a simple CR filter for DC removal though if the board is already fabricated and your only 'free parameter' is the FPGA it may not be an option. Good luck, Dave.
Reply by ●June 23, 20052005-06-23
ytregubov@yahoo.com wrote:> Use highpass filter. > > Regards, > Yuri >That's a really bad idea. A filter cutting off very low in the band is not nice. Estimating the DC and subtracting it is the right approach. Regards, Steve
Reply by ●June 23, 20052005-06-23
in article d9eedv$lt1$1@nnews.pacific.net.hk, Steve Underwood at steveu@dis.org wrote on 06/23/2005 09:39:> ytregubov@yahoo.com wrote: >> Use highpass filter. >> >> Regards, >> Yuri >> > That's a really bad idea. A filter cutting off very low in the band is > not nice. Estimating the DC and subtracting it is the right approach.but Steve, if it's a continuous running real-time system, how do you continuously estimate DC? only way i know is with a LPF. then when you take the "DC" output of the LPF and subtract it from the input signal, what functionally have is an HPF. now there are many different HPFs with different orders and cutoff frequencies and filter shape, etc. but essentially, when you do DC blocking, you're doing HPFing. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge."
Reply by ●June 23, 20052005-06-23
shridhar@mistralsoftware.com wrote:> Hi, > > we are reading an ADC o/p through FPGA. To remove the DC Offset present > in the ADC input we have a DAC which can remove this DC offset using a > subtractor before the actual analog input (with added DC offset) goes > to ADC. > > Now I want my FPGA to calculate the DC offset from ADC outputs and then > feed this value to DAC input which in turn cancel the DC offset using > subtrator. > > can anybody suggest me how can i implement this in FPGA? I just gone > through net and realized that i can use a subtractor and a MAC. The ADC > output will go to this Subtractor which has the final output of MAC as > other input. the subtractor output will be multiplied with some small > value K (??) and then an accumulator. The final output of accumulator > can be feedback to the DAC. The DAC o/p is going to Mixer to cancel the > DC offset? > > this is what i understood. can somebody through some light? > > suggestions are welcome. >You simply need to integrate the ADC reading and apply the integrated and scaled answer back to the DAC. As long as the ADC value does not average out to zero it's integral will climb or descend, which will keep changing the command to the DAC. When the ADC value _does_ average to zero then the DAC command will cease changing. As Dave Coffey mentioned you don't even need to do an explicit multiplication -- you can just use shifts. Your biggest challenge will be verifying just how slowly you want to remove DC offet, and scaling your shift appropriately. I suspect you want to set the shift to be larger than the bit count of the ADC, and probably significantly more, to avoid the LSB of the DAC moving around -- but that's your call. So make a register that's big enough, and whenever you sample your ADC add it's value (appropriately sign extended, of course) to the ADC, then apply a shifted version to the DAC: // Note this is verilog, more or less DacValue <= register >> `DAC_SHIFT; // Scale the output register <= register + AdcValue; // capture all the input As written there's a one-cycle delay in the writing of the DAC value -- this should have a negligible impact on the process because it's so slow. In fact you should be able to pipeline this to a great extent, because you want to have a very slow process which implies a great tolerance for delay. -- ------------------------------------------- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●June 23, 20052005-06-23
robert bristow-johnson wrote:> in article d9eedv$lt1$1@nnews.pacific.net.hk, Steve Underwood at > steveu@dis.org wrote on 06/23/2005 09:39: > > >>ytregubov@yahoo.com wrote: >> >>>Use highpass filter. >>> >>>Regards, >>>Yuri >>> >> >>That's a really bad idea. A filter cutting off very low in the band is >>not nice. Estimating the DC and subtracting it is the right approach. > > > but Steve, if it's a continuous running real-time system, how do you > continuously estimate DC? only way i know is with a LPF. then when you > take the "DC" output of the LPF and subtract it from the input signal, what > functionally have is an HPF. > > now there are many different HPFs with different orders and cutoff > frequencies and filter shape, etc. but essentially, when you do DC > blocking, you're doing HPFing. >Sure. A low pass filter and subtraction gives a high pass filter. However, when someone says use a high pass filter, and the previous post talked about subtracting a DC estimate, I rather think they mean a direct HPF implementation. Regards, Steve
Reply by ●June 23, 20052005-06-23
in article d9eqq5$5b2$1@nnews.pacific.net.hk, Steve Underwood at steveu@dis.org wrote on 06/23/2005 13:11:> robert bristow-johnson wrote: >> in article d9eedv$lt1$1@nnews.pacific.net.hk, Steve Underwood at >> steveu@dis.org wrote on 06/23/2005 09:39: >> >> >>> ytregubov@yahoo.com wrote: >>> >>>> Use highpass filter. >>>> >>>> Regards, >>>> Yuri >>>> >>> >>> That's a really bad idea. A filter cutting off very low in the band is >>> not nice. Estimating the DC and subtracting it is the right approach. >> >> >> but Steve, if it's a continuous running real-time system, how do you >> continuously estimate DC? only way i know is with a LPF. then when you >> take the "DC" output of the LPF and subtract it from the input signal, what >> functionally have is an HPF. >> >> now there are many different HPFs with different orders and cutoff >> frequencies and filter shape, etc. but essentially, when you do DC >> blocking, you're doing HPFing. >> > Sure. A low pass filter and subtraction gives a high pass filter. > However, when someone says use a high pass filter, and the previous post > talked about subtracting a DC estimate, I rather think they mean a > direct HPF implementation.so now i beg the question: so what? what's the difference? if they use an LPF to get the DC and subtract that "DC" from the signal, they have an HPF which would perform identically to the "direct HPF implementation" so designed. same H(z) in both cases. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge."
Reply by ●June 26, 20052005-06-26
