Connecting TigerSharc TS201 EzKIT to PCI with Spartan 3

Hello.

I want to control an ADSP-TS201S EZ-KIT Lite from a PC by connecting it
to an Avnet evaluation kit which contains a Spartan 3 on a PCI form
factor through one of the EZ-KIT link ports pairs. My application data
throughput is not very demanding so it=B4s my understanding I can
program the SPD bits to divide the 500MHz CCLK by 4 giving me a
transfer clock of 125MHz (transfer rate of 250Mbps) wich is much higher
than I need (I wish I could reduce it even more - 100 or even 50MBps
would do just fine). So my first question is if Spartan 3 (-4 grade to
stay in the worst case) would allow such a rate reliably. May I clock
the receiving side at a lower rate then the trasmitter?

I also would like to know if somebody could indicate resources other
than Xilinx=B4s xapp634/xapp635, including commercial cores. Google
hasn=B4t been of much help unfortunately. I am also considering other
ways (Bittware=B4s ASIC, AMCC=B4s Matchmaker etc.) to do the final design
but the scheme above seems to be the simplest that would allow me to
develop with TS before I have a workable prototype (I may be missing
something though and would appreciate your inputs.)  If it works fine I
may even use it in the final design as it=B4s going to have a FPGA (much
likely a Spartan 3) anyway.

Thank you very much in advance for your insights.

Elder.

Transtech DSP were doing stuff with tigersharcs and FPGAs. It was some
time ago that I looked but I'm fairly certain I saw a block diagram
with a link going to an FPGA.

Elder Costa wrote:
> Hello.
>
> I want to control an ADSP-TS201S EZ-KIT Lite from a PC by connecting it
> to an Avnet evaluation kit which contains a Spartan 3 on a PCI form
> factor through one of the EZ-KIT link ports pairs. My application data
> throughput is not very demanding so it=B4s my understanding I can
> program the SPD bits to divide the 500MHz CCLK by 4 giving me a
> transfer clock of 125MHz (transfer rate of 250Mbps) wich is much higher
> than I need (I wish I could reduce it even more - 100 or even 50MBps
> would do just fine). So my first question is if Spartan 3 (-4 grade to
> stay in the worst case) would allow such a rate reliably. May I clock
> the receiving side at a lower rate then the trasmitter?
>
> I also would like to know if somebody could indicate resources other
> than Xilinx=B4s xapp634/xapp635, including commercial cores. Google
> hasn=B4t been of much help unfortunately. I am also considering other
> ways (Bittware=B4s ASIC, AMCC=B4s Matchmaker etc.) to do the final design
> but the scheme above seems to be the simplest that would allow me to
> develop with TS before I have a workable prototype (I may be missing
> something though and would appreciate your inputs.)  If it works fine I
> may even use it in the final design as it=B4s going to have a FPGA (much
> likely a Spartan 3) anyway.
>=20
> Thank you very much in advance for your insights.
>=20
> Elder.