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C6713 DSK problem

Started by karthik_n August 8, 2005
Hello everyone,

I am working with a Spectrum Digital C6713 DSK, and I have a seemingly
bizarre problem. I have a program that does some write cycles to the CE2
space. I run the program in two different ways.
1. I load the .out file through CCS, and run it from internal memory.
2. I generate a hex file, burn the flash, and bootload from flash.

The program behaves differently in the two cases. When I load it through
CCS, I see the output I expect(basically a UART stream on the daughter
card), but when I bootload from flash, nothing happens. I have matched my
EMIF initialization in my boot file with the DSK6713 GEL file. But, I'm
missing something here. The programs should behave the same in both the
cases. Here is the boot file that I'm using. I appreciate any thoughts on
this. Thanks.

BOOT SOURCE FILE
----------------

;
;  ======== boot_c671x.s62 ========
;
            .title  "Flash bootup utility"
            .option D,T
            .length 102
            .width  140

; global EMIF symbols defined for the c671x family
            .include        boot_c671x.h62

STRAP_BUFFER  .equ    0xA0000080        ;strapping input buffer address
            .sect ".boot_load"
            .global _boot
            
            ;.global _text_size
            ;.global _text_ld_start
            ;.global _text_rn_start
            
            .ref _c_int00      
            
_boot:      
;************************************************************************
;* DEBUG LOOP -  COMMENT OUT B FOR NORMAL OPERATION
;************************************************************************

            zero B1
_myloop:   ;[!B1] B _myloop  
            nop  5
_myloopend: nop

;************************************************************************
;* CONFIGURE EMIF
;************************************************************************

        ;****************************************************************
        ; *EMIF_GCTL = EMIF_GCTL_V;
        ;****************************************************************

            mvkl  EMIF_GCTL,A4    
      ||    mvkl  EMIF_GCTL_V,B4

            mvkh  EMIF_GCTL,A4
      ||    mvkh  EMIF_GCTL_V,B4

            stw   B4,*A4

        ;****************************************************************
        ; *EMIF_CE0 = EMIF_CE0_V
        ;****************************************************************

            mvkl  EMIF_CE0,A4       
      ||    mvkl  EMIF_CE0_V,B4     

            mvkh  EMIF_CE0,A4
      ||    mvkh  EMIF_CE0_V,B4

            stw   B4,*A4

        ;****************************************************************
        ; *EMIF_CE1 = EMIF_CE1_V (setup for 8-bit async)
        ;****************************************************************

            mvkl  EMIF_CE1,A4       
      ||    mvkl  EMIF_CE1_V,B4

            mvkh  EMIF_CE1,A4
      ||    mvkh  EMIF_CE1_V,B4

            stw   B4,*A4
        
        ;****************************************************************
        ; *EMIF_CE2 = EMIF_CE2_V (setup for 32-bit async)
        ;****************************************************************

            mvkl  EMIF_CE2,A4       
      ||    mvkl  EMIF_CE2_V,B4

            mvkh  EMIF_CE2,A4
      ||    mvkh  EMIF_CE2_V,B4

            stw   B4,*A4

        ;****************************************************************
        ; *EMIF_CE3 = EMIF_CE3_V (setup for 32-bit async)
        ;****************************************************************

      ||    mvkl  EMIF_CE3,A4    
      ||    mvkl  EMIF_CE3_V,B4     ;

            mvkh  EMIF_CE3,A4
      ||    mvkh  EMIF_CE3_V,B4

            stw   B4,*A4

        ;****************************************************************
        ; *EMIF_SDRAMCTL = EMIF_SDRAMCTL_V
        ;****************************************************************
      ||    mvkl  EMIF_SDRAMCTL,A4      
      ||    mvkl  EMIF_SDRAMCTL_V,B4    ;

            mvkh  EMIF_SDRAMCTL,A4
      ||    mvkh  EMIF_SDRAMCTL_V,B4

            stw   B4,*A4

        ;****************************************************************
        ; *EMIF_SDRAMTIM = EMIF_SDRAMTIM_V
        ;****************************************************************
      ||    mvkl  EMIF_SDRAMTIM,A4      
      ||    mvkl  EMIF_SDRAMTIM_V,B4    ;

            mvkh  EMIF_SDRAMTIM,A4
      ||    mvkh  EMIF_SDRAMTIM_V,B4

            stw   B4,*A4

        ;****************************************************************
        ; *EMIF_SDRAMEXT = EMIF_SDRAMEXT_V
        ;****************************************************************
      ||    mvkl  EMIF_SDRAMEXT,A4      
      ||    mvkl  EMIF_SDRAMEXT_V,B4    ;

            mvkh  EMIF_SDRAMEXT,A4
      ||    mvkh  EMIF_SDRAMEXT_V,B4

            stw   B4,*A4

;READ CAL1 and CAL2 strap inputs to decide which code to copy
_boot_start:
        
        ;read CAL1 and CAL2 strap inputs and decide
        ;the code(normal or factory) to load

        mvkl  STRAP_BUFFER,B4           ;strap address in B4
        mvkh  STRAP_BUFFER,B4                 

        ldw   *B4,B5                 ;read strap buffer to B5 - load
16-bits 
        nop 4
        zero B6
        mvkl   1000h,B6              ;mask value for CAL2 and CAL1 -
actual val 3000
        and   B6,B5,B5               ;mask CAL1 and CAL2(bits 12 and 13)
        shru  B5,12,B6               ;CAL2:1 in B6(1:0)
        cmpeq 1,B6,B0                ;B0 = 0 -> load normal code
        nop 5                        ;B0 = 1 -> load factory code

        ;;to be removed later
        ;zero B0
        ;add   1,B0,B0          ;B0+=1,inc outer counter
        ;;;;;;;;


        [!B0]   b     _normal_boot   ;if B0=0[CAL1=0,CAL2=0],perform
normal boot
        nop 5
        [B0] b     _normal_boot;[B0] b     _factory_boot     ;if
B0=1[CAL1=1,CAL2=0],perform factory boot  
        nop 5

;!!!!IMPORTANT!!!!! - CODE SIZES OF NORMAL AND FACTORY ARE ASSUMED TO BE
THE SAME HERE !!!!!!!

_normal_boot:
        mvkl  normalTable, a3 ; load table pointer
        mvkh  normalTable, a3
                  
        b     copy_section_top    	
        nop 5
        
  
_factory_boot:
        mvkl  factoryTable, a3 ; load table pointer
        mvkh  factoryTable, a3
        
;_boot_code:

;    ldw   *a3++, b6     ; byte count 
;    ldw   *a3++, b4     ; load flash start (load) address 
;    ldw   *a3++, a4     ; ram start address

	;mvkl  CODE_START,A4 ;apps code start address ->A4
	;mvkh  CODE_START,A4
;	zero  A1
	
;_boot_loop1:
;	ldb   *B4++,B5       ; flash read
	;mvkl  CODE_SIZE-4,B6 ; B6 = BOOT_SIZE -1024
	   
;	add   1,A1,A1          ;A1+=1,inc outer counter
	;||    mvkh  CODE_SIZE-4,B6  ;is this needed????
	
;	cmplt  A1,B6,B0
;	nop    
;	stb   B5,*A4++
;	[B0]  b     _boot_loop1
;	nop   5

;****************************************************************************
; jump to entry point
;****************************************************************************
;copy_done:
;		mvkl .S2 _c_int00, B0
;        mvkh .S2 _c_int00, B0
;        b    .S2 B0
;        nop   5


;****************************************************************************
; copy sections
;****************************************************************************
;        mvkl  copyTable, a3 ; load table pointer
;        mvkh  copyTable, a3

    
copy_section_top:
        ldw   *a3++, b0     ; byte count 
        ldw   *a3++, b4     ; load flash start (load) address 
        ldw   *a3++, a4     ; ram start address
        nop   2             

 [!b0]  b copy_done         ; have we copied all sections?
        nop   5

copy_loop:
        ldb   *b4++,b5      
        sub   b0,1,b0       ; decrement counter
 [ b0]  b     copy_loop     ; setup branch if not done
 [!b0]  b     copy_section_top
        zero  a1
 [!b0]  and   3,a3,a1
        stb   b5,*a4++
 [!b0]  and   -4,a3,a5      ; round address up to next multiple of 4
 [ a1]  add   4,a5,a3       ; round address up to next multiple of 4

;****************************************************************************
; jump to entry point
;****************************************************************************
copy_done:
		mvkl .S2 _c_int00, B0
        mvkh .S2 _c_int00, B0
        b    .S2 B0
        nop   5

;copyTable: 
	
			; count
			; flash start (load) address 
			; ram start (run) address
	 
    		;; .text
    		;.word _text_size
    		;.word _text_ld_start
    		;.word _text_rn_start
    
;            .word 0x000024a0     ;text size
;            .word 0x90000400     ;flash load address(load address)
;            .word 0x00000400     ;ram start address(run address)
    
		      		
    		;; end of table
;    		.word 0
;    		.word 0
;    		.word 0
 
normalTable: 
	
			; count
			; flash start (load) address 
			; ram start (run) address
            .word 0x00005020     ;text size
            .word 0x90000400     ;flash load address(load address)
            .word 0x00000400     ;ram start address(run address)
            ;table end
            .word 0
     		.word 0
    		.word 0
    
    
factoryTable: 
	
			; count
			; flash start (load) address 
			; ram start (run) address
            .word 0x000024a0     ;text size
            .word 0x90010000     ;flash load address(load address)
            .word 0x00000400     ;ram start address(run address)
            ;table end
            .word 0
     		.word 0
    		.word 0 
             
		      		
    		;; end of table
;    		.word 0
;    		.word 0
;    		.word 0     


/*** C6713 EMIF file ****/
;
            .title  "Flash bootup utility"

; global EMIF symbols defined for the c671x family
            .include        boot_c671x.h62

;EMIF Register Addresses for c671x family  
EMIF_GCTL       .equ  0x01800000  ;EMIF global control
EMIF_CE1        .equ  0x01800004  ;address of EMIF CE1 control reg.
EMIF_CE0        .equ  0x01800008  ;EMIF CE0control
EMIF_CE2        .equ  0x01800010  ;EMIF CE2control
EMIF_CE3        .equ  0x01800014  ;EMIF CE3control
EMIF_SDRAMCTL   .equ  0x01800018  ;EMIF SDRAM control
EMIF_SDRAMTIM   .equ  0x0180001c  ;EMIF SDRAM timer
EMIF_SDRAMEXT   .equ  0x01800020  ;EMIF SDRAM extension

; EMIF Register Values specifically for 6713 DSK
EMIF_GCTL_V     .equ  0x00000068;0x00000078  ;
EMIF_CE0_V      .equ  0xffffbf33  ;EMIF CE0 SDRAM
EMIF_CE1_V      .equ  0x02208802  ;EMIF CE1 Flash 8-bit
EMIF_CE2_V      .equ  0xffffbf23  ;0x22a28a22  ;EMIF CE2 Daughtercard
32-bit async
EMIF_CE3_V      .equ  0x22a28a22  ;EMIF CE3 Daughtercard 32-bit async
EMIF_SDRAMCTL_V .equ  0x47115000  ;EMIF SDRAM control
EMIF_SDRAMTIM_V .equ  0x00000578  ;SDRAM timing (refresh)
EMIF_SDRAMEXT_V .equ  0x000a8529  ;SDRAM extended control






		
This message was sent using the Comp.DSP web interface on
www.DSPRelated.com
We use the 6713DSK in the Control Systems Lab at the Univerity of
Illinois.  My current source code is at
http://coecsl.ece.uiuc.edu/ge423/source/c6713dsk/project_creator/ge423/
If you have VB on your computer you can run my "project_creator" to
create a new project ready to be flashed on the DSK.  Of course you
will need to delete a number of things from my source code since you do
not have the daughter card attached to our system.


karthik_n wrote:
> Hello everyone, > > I am working with a Spectrum Digital C6713 DSK, and I have a seemingly > bizarre problem. I have a program that does some write cycles to the CE2 > space. I run the program in two different ways. > 1. I load the .out file through CCS, and run it from internal memory. > 2. I generate a hex file, burn the flash, and bootload from flash. > > The program behaves differently in the two cases. When I load it through > CCS, I see the output I expect(basically a UART stream on the daughter > card), but when I bootload from flash, nothing happens. I have matched my > EMIF initialization in my boot file with the DSK6713 GEL file. But, I'm > missing something here. The programs should behave the same in both the > cases. Here is the boot file that I'm using. I appreciate any thoughts on > this. Thanks. > > BOOT SOURCE FILE > ---------------- > > ; > ; ======== boot_c671x.s62 ======== > ; > .title "Flash bootup utility" > .option D,T > .length 102 > .width 140 > > ; global EMIF symbols defined for the c671x family > .include boot_c671x.h62 > > STRAP_BUFFER .equ 0xA0000080 ;strapping input buffer address > .sect ".boot_load" > .global _boot > > ;.global _text_size > ;.global _text_ld_start > ;.global _text_rn_start > > .ref _c_int00 > > _boot: > ;************************************************************************ > ;* DEBUG LOOP - COMMENT OUT B FOR NORMAL OPERATION > ;************************************************************************ > > zero B1 > _myloop: ;[!B1] B _myloop > nop 5 > _myloopend: nop > > ;************************************************************************ > ;* CONFIGURE EMIF > ;************************************************************************ > > ;**************************************************************** > ; *EMIF_GCTL = EMIF_GCTL_V; > ;**************************************************************** > > mvkl EMIF_GCTL,A4 > || mvkl EMIF_GCTL_V,B4 > > mvkh EMIF_GCTL,A4 > || mvkh EMIF_GCTL_V,B4 > > stw B4,*A4 > > ;**************************************************************** > ; *EMIF_CE0 = EMIF_CE0_V > ;**************************************************************** > > mvkl EMIF_CE0,A4 > || mvkl EMIF_CE0_V,B4 > > mvkh EMIF_CE0,A4 > || mvkh EMIF_CE0_V,B4 > > stw B4,*A4 > > ;**************************************************************** > ; *EMIF_CE1 = EMIF_CE1_V (setup for 8-bit async) > ;**************************************************************** > > mvkl EMIF_CE1,A4 > || mvkl EMIF_CE1_V,B4 > > mvkh EMIF_CE1,A4 > || mvkh EMIF_CE1_V,B4 > > stw B4,*A4 > > ;**************************************************************** > ; *EMIF_CE2 = EMIF_CE2_V (setup for 32-bit async) > ;**************************************************************** > > mvkl EMIF_CE2,A4 > || mvkl EMIF_CE2_V,B4 > > mvkh EMIF_CE2,A4 > || mvkh EMIF_CE2_V,B4 > > stw B4,*A4 > > ;**************************************************************** > ; *EMIF_CE3 = EMIF_CE3_V (setup for 32-bit async) > ;**************************************************************** > > || mvkl EMIF_CE3,A4 > || mvkl EMIF_CE3_V,B4 ; > > mvkh EMIF_CE3,A4 > || mvkh EMIF_CE3_V,B4 > > stw B4,*A4 > > ;**************************************************************** > ; *EMIF_SDRAMCTL = EMIF_SDRAMCTL_V > ;**************************************************************** > || mvkl EMIF_SDRAMCTL,A4 > || mvkl EMIF_SDRAMCTL_V,B4 ; > > mvkh EMIF_SDRAMCTL,A4 > || mvkh EMIF_SDRAMCTL_V,B4 > > stw B4,*A4 > > ;**************************************************************** > ; *EMIF_SDRAMTIM = EMIF_SDRAMTIM_V > ;**************************************************************** > || mvkl EMIF_SDRAMTIM,A4 > || mvkl EMIF_SDRAMTIM_V,B4 ; > > mvkh EMIF_SDRAMTIM,A4 > || mvkh EMIF_SDRAMTIM_V,B4 > > stw B4,*A4 > > ;**************************************************************** > ; *EMIF_SDRAMEXT = EMIF_SDRAMEXT_V > ;**************************************************************** > || mvkl EMIF_SDRAMEXT,A4 > || mvkl EMIF_SDRAMEXT_V,B4 ; > > mvkh EMIF_SDRAMEXT,A4 > || mvkh EMIF_SDRAMEXT_V,B4 > > stw B4,*A4 > > ;READ CAL1 and CAL2 strap inputs to decide which code to copy > _boot_start: > > ;read CAL1 and CAL2 strap inputs and decide > ;the code(normal or factory) to load > > mvkl STRAP_BUFFER,B4 ;strap address in B4 > mvkh STRAP_BUFFER,B4 > > ldw *B4,B5 ;read strap buffer to B5 - load > 16-bits > nop 4 > zero B6 > mvkl 1000h,B6 ;mask value for CAL2 and CAL1 - > actual val 3000 > and B6,B5,B5 ;mask CAL1 and CAL2(bits 12 and 13) > shru B5,12,B6 ;CAL2:1 in B6(1:0) > cmpeq 1,B6,B0 ;B0 = 0 -> load normal code > nop 5 ;B0 = 1 -> load factory code > > ;;to be removed later > ;zero B0 > ;add 1,B0,B0 ;B0+=1,inc outer counter > ;;;;;;;; > > > [!B0] b _normal_boot ;if B0=0[CAL1=0,CAL2=0],perform > normal boot > nop 5 > [B0] b _normal_boot;[B0] b _factory_boot ;if > B0=1[CAL1=1,CAL2=0],perform factory boot > nop 5 > > ;!!!!IMPORTANT!!!!! - CODE SIZES OF NORMAL AND FACTORY ARE ASSUMED TO BE > THE SAME HERE !!!!!!! > > _normal_boot: > mvkl normalTable, a3 ; load table pointer > mvkh normalTable, a3 > > b copy_section_top > nop 5 > > > _factory_boot: > mvkl factoryTable, a3 ; load table pointer > mvkh factoryTable, a3 > > ;_boot_code: > > ; ldw *a3++, b6 ; byte count > ; ldw *a3++, b4 ; load flash start (load) address > ; ldw *a3++, a4 ; ram start address > > ;mvkl CODE_START,A4 ;apps code start address ->A4 > ;mvkh CODE_START,A4 > ; zero A1 > > ;_boot_loop1: > ; ldb *B4++,B5 ; flash read > ;mvkl CODE_SIZE-4,B6 ; B6 = BOOT_SIZE -1024 > > ; add 1,A1,A1 ;A1+=1,inc outer counter > ;|| mvkh CODE_SIZE-4,B6 ;is this needed???? > > ; cmplt A1,B6,B0 > ; nop > ; stb B5,*A4++ > ; [B0] b _boot_loop1 > ; nop 5 > > ;**************************************************************************** > ; jump to entry point > ;**************************************************************************** > ;copy_done: > ; mvkl .S2 _c_int00, B0 > ; mvkh .S2 _c_int00, B0 > ; b .S2 B0 > ; nop 5 > > > ;**************************************************************************** > ; copy sections > ;**************************************************************************** > ; mvkl copyTable, a3 ; load table pointer > ; mvkh copyTable, a3 > > > copy_section_top: > ldw *a3++, b0 ; byte count > ldw *a3++, b4 ; load flash start (load) address > ldw *a3++, a4 ; ram start address > nop 2 > > [!b0] b copy_done ; have we copied all sections? > nop 5 > > copy_loop: > ldb *b4++,b5 > sub b0,1,b0 ; decrement counter > [ b0] b copy_loop ; setup branch if not done > [!b0] b copy_section_top > zero a1 > [!b0] and 3,a3,a1 > stb b5,*a4++ > [!b0] and -4,a3,a5 ; round address up to next multiple of 4 > [ a1] add 4,a5,a3 ; round address up to next multiple of 4 > > ;**************************************************************************** > ; jump to entry point > ;**************************************************************************** > copy_done: > mvkl .S2 _c_int00, B0 > mvkh .S2 _c_int00, B0 > b .S2 B0 > nop 5 > > ;copyTable: > > ; count > ; flash start (load) address > ; ram start (run) address > > ;; .text > ;.word _text_size > ;.word _text_ld_start > ;.word _text_rn_start > > ; .word 0x000024a0 ;text size > ; .word 0x90000400 ;flash load address(load address) > ; .word 0x00000400 ;ram start address(run address) > > > ;; end of table > ; .word 0 > ; .word 0 > ; .word 0 > > normalTable: > > ; count > ; flash start (load) address > ; ram start (run) address > .word 0x00005020 ;text size > .word 0x90000400 ;flash load address(load address) > .word 0x00000400 ;ram start address(run address) > ;table end > .word 0 > .word 0 > .word 0 > > > factoryTable: > > ; count > ; flash start (load) address > ; ram start (run) address > .word 0x000024a0 ;text size > .word 0x90010000 ;flash load address(load address) > .word 0x00000400 ;ram start address(run address) > ;table end > .word 0 > .word 0 > .word 0 > > > ;; end of table > ; .word 0 > ; .word 0 > ; .word 0 > > > /*** C6713 EMIF file ****/ > ; > .title "Flash bootup utility" > > ; global EMIF symbols defined for the c671x family > .include boot_c671x.h62 > > ;EMIF Register Addresses for c671x family > EMIF_GCTL .equ 0x01800000 ;EMIF global control > EMIF_CE1 .equ 0x01800004 ;address of EMIF CE1 control reg. > EMIF_CE0 .equ 0x01800008 ;EMIF CE0control > EMIF_CE2 .equ 0x01800010 ;EMIF CE2control > EMIF_CE3 .equ 0x01800014 ;EMIF CE3control > EMIF_SDRAMCTL .equ 0x01800018 ;EMIF SDRAM control > EMIF_SDRAMTIM .equ 0x0180001c ;EMIF SDRAM timer > EMIF_SDRAMEXT .equ 0x01800020 ;EMIF SDRAM extension > > ; EMIF Register Values specifically for 6713 DSK > EMIF_GCTL_V .equ 0x00000068;0x00000078 ; > EMIF_CE0_V .equ 0xffffbf33 ;EMIF CE0 SDRAM > EMIF_CE1_V .equ 0x02208802 ;EMIF CE1 Flash 8-bit > EMIF_CE2_V .equ 0xffffbf23 ;0x22a28a22 ;EMIF CE2 Daughtercard > 32-bit async > EMIF_CE3_V .equ 0x22a28a22 ;EMIF CE3 Daughtercard 32-bit async > EMIF_SDRAMCTL_V .equ 0x47115000 ;EMIF SDRAM control > EMIF_SDRAMTIM_V .equ 0x00000578 ;SDRAM timing (refresh) > EMIF_SDRAMEXT_V .equ 0x000a8529 ;SDRAM extended control > > > > > > > > This message was sent using the Comp.DSP web interface on > www.DSPRelated.com