Forums

Undersampling of a clean carrier

Started by Paul Solomon August 31, 2005
Hi,

I have just been doing some test and I noticed a concerning problem that I 
may be having with the undersampling design (for FM demod).

I basically set up my board so that the adc input (which is clocked at 
80MHz) feeds directly into a DAC also clocked at 80MHz.

If I put a 20MHz tone (clean sine wave CW) on the input (from a signal 
generator) I get a clean 20MHz tone present on the output of the DAC when I 
look at it ona spectrum analyser. The output shows about 60dB Signal to the 
first intermod which is at 20.235 MHz..

If I put a 100MHz tone into the ADC input, I was expecting a similar result 
as there is no other signals in the present, so this should appear as a 
clead 20MHz carrier on the DAC output. However on the output I do get my 
20MHz carrier, but the SNR reduced to 35dB to the first intermod at 
20.235MHz and there appears to be a lot of phase noise arond the carrier.

I have checked and double checked the input signals and they are very clean 
showing about 80dB SNR (which is the max I can see on the spec an anyway).

The bitwidth of the ADC is 12 bits and the DAC is 14 bits. The ADC is 2's 
compliment and the DAC is unsigned. So to connect the ADC to the DAC I have 
basically got.

DAC[13] = ~ADC[11];
DAC[12] = ADC[10];
DAC[11] = ADC[9];
DAC[10] = ADC[8];
DAC[9] = ADC[7];
DAC[8] = ADC[6];
DAC[7] = ADC[5];
DAC[6] = ADC[4];
DAC[5] = ADC[3];
DAC[4] = ADC[2];
DAC[3] = ADC[1];
DAC[2] = ADC[0];
DAC[1] = 0;
DAC[0] = 0;

the MSB is inverted to convert from signed to unsigned.

Do these results sound like what you would expect to see or can anyone see 
what I could be doing wrong here? I was not expecting an undersampled signal 
to have such poor SNR.

Regards,

Paul Solomon 


Hi Paul,
You might like to read this AD app note:
"Aperture Uncertainty and ADC System Performance"
http://www.analog.com/UploadedFiles/Application_Notes/5356940929547373956522730668848977365163734AN501.pdf

Phase noise of the sampling clock may also be a problem.

Regards,
Allan

I would also check to make sure that the sample and hold bandwidth of
the ADC is more then 100 MHz.
After that, I would modify the board to check the signal quality at the
ADC input at 100 MHz, and to check the RF path for the DAC output at
100 MHz.

Check your full power bandwidth of your ADC and make sure it is well above 
100 MHz, and don't forget that the clock jitter (phase noise) is exaggerated 
the higher in input frequency you go.

Other than that, you can look at the timing synchronization between the ADC 
and the DAC. It shouldn't be effected if your not changing the sample rate 
but who knows, you might be boarder line and dropping bits for some reason.

Thomas

"Paul Solomon" <psolomon@tpg.com.au> wrote in message 
news:4316590d@dnews.tpgi.com.au...
> Hi, > > I have just been doing some test and I noticed a concerning problem that I > may be having with the undersampling design (for FM demod). > > I basically set up my board so that the adc input (which is clocked at > 80MHz) feeds directly into a DAC also clocked at 80MHz. > > If I put a 20MHz tone (clean sine wave CW) on the input (from a signal > generator) I get a clean 20MHz tone present on the output of the DAC when > I look at it ona spectrum analyser. The output shows about 60dB Signal to > the first intermod which is at 20.235 MHz.. > > If I put a 100MHz tone into the ADC input, I was expecting a similar > result as there is no other signals in the present, so this should appear > as a clead 20MHz carrier on the DAC output. However on the output I do get > my 20MHz carrier, but the SNR reduced to 35dB to the first intermod at > 20.235MHz and there appears to be a lot of phase noise arond the carrier. > > I have checked and double checked the input signals and they are very > clean showing about 80dB SNR (which is the max I can see on the spec an > anyway). > > The bitwidth of the ADC is 12 bits and the DAC is 14 bits. The ADC is 2's > compliment and the DAC is unsigned. So to connect the ADC to the DAC I > have basically got. > > DAC[13] = ~ADC[11]; > DAC[12] = ADC[10]; > DAC[11] = ADC[9]; > DAC[10] = ADC[8]; > DAC[9] = ADC[7]; > DAC[8] = ADC[6]; > DAC[7] = ADC[5]; > DAC[6] = ADC[4]; > DAC[5] = ADC[3]; > DAC[4] = ADC[2]; > DAC[3] = ADC[1]; > DAC[2] = ADC[0]; > DAC[1] = 0; > DAC[0] = 0; > > the MSB is inverted to convert from signed to unsigned. > > Do these results sound like what you would expect to see or can anyone see > what I could be doing wrong here? I was not expecting an undersampled > signal to have such poor SNR. > > Regards, > > Paul Solomon >
"Paul Solomon" <psolomon@tpg.com.au> wrote in message 
news:4316590d@dnews.tpgi.com.au...
> Hi, > > I have just been doing some test and I noticed a concerning problem that I > may be having with the undersampling design (for FM demod). > > I basically set up my board so that the adc input (which is clocked at > 80MHz) feeds directly into a DAC also clocked at 80MHz. > > If I put a 20MHz tone (clean sine wave CW) on the input (from a signal > generator) I get a clean 20MHz tone present on the output of the DAC when > I look at it ona spectrum analyser. The output shows about 60dB Signal to > the first intermod which is at 20.235 MHz.. > > If I put a 100MHz tone into the ADC input, I was expecting a similar > result as there is no other signals in the present, so this should appear > as a clead 20MHz carrier on the DAC output. However on the output I do get > my 20MHz carrier, but the SNR reduced to 35dB to the first intermod at > 20.235MHz and there appears to be a lot of phase noise arond the carrier. > > I have checked and double checked the input signals and they are very > clean showing about 80dB SNR (which is the max I can see on the spec an > anyway). > > The bitwidth of the ADC is 12 bits and the DAC is 14 bits. The ADC is 2's > compliment and the DAC is unsigned. So to connect the ADC to the DAC I > have basically got. > > DAC[13] = ~ADC[11]; > DAC[12] = ADC[10]; > DAC[11] = ADC[9]; > DAC[10] = ADC[8]; > DAC[9] = ADC[7]; > DAC[8] = ADC[6]; > DAC[7] = ADC[5]; > DAC[6] = ADC[4]; > DAC[5] = ADC[3]; > DAC[4] = ADC[2]; > DAC[3] = ADC[1]; > DAC[2] = ADC[0]; > DAC[1] = 0; > DAC[0] = 0; > > the MSB is inverted to convert from signed to unsigned. > > Do these results sound like what you would expect to see or can anyone see > what I could be doing wrong here? I was not expecting an undersampled > signal to have such poor SNR. > > Regards, > > Paul Solomon >
Did you find where the problem was? I'm kind of curious as to where the source of your problems were.
"Thomas Magma" <somewhere@overtherainbow.com> wrote in message 
news:dXiTe.402841$5V4.32336@pd7tw3no...
> > "Paul Solomon" <psolomon@tpg.com.au> wrote in message > news:4316590d@dnews.tpgi.com.au... >> Hi, >> >> I have just been doing some test and I noticed a concerning problem that >> I may be having with the undersampling design (for FM demod). >> >> I basically set up my board so that the adc input (which is clocked at >> 80MHz) feeds directly into a DAC also clocked at 80MHz. >> >> If I put a 20MHz tone (clean sine wave CW) on the input (from a signal >> generator) I get a clean 20MHz tone present on the output of the DAC when >> I look at it ona spectrum analyser. The output shows about 60dB Signal to >> the first intermod which is at 20.235 MHz.. >> >> If I put a 100MHz tone into the ADC input, I was expecting a similar >> result as there is no other signals in the present, so this should appear >> as a clead 20MHz carrier on the DAC output. However on the output I do >> get my 20MHz carrier, but the SNR reduced to 35dB to the first intermod >> at 20.235MHz and there appears to be a lot of phase noise arond the >> carrier. >> >> I have checked and double checked the input signals and they are very >> clean showing about 80dB SNR (which is the max I can see on the spec an >> anyway). >> >> The bitwidth of the ADC is 12 bits and the DAC is 14 bits. The ADC is 2's >> compliment and the DAC is unsigned. So to connect the ADC to the DAC I >> have basically got. >> >> DAC[13] = ~ADC[11]; >> DAC[12] = ADC[10]; >> DAC[11] = ADC[9]; >> DAC[10] = ADC[8]; >> DAC[9] = ADC[7]; >> DAC[8] = ADC[6]; >> DAC[7] = ADC[5]; >> DAC[6] = ADC[4]; >> DAC[5] = ADC[3]; >> DAC[4] = ADC[2]; >> DAC[3] = ADC[1]; >> DAC[2] = ADC[0]; >> DAC[1] = 0; >> DAC[0] = 0; >> >> the MSB is inverted to convert from signed to unsigned. >> >> Do these results sound like what you would expect to see or can anyone >> see what I could be doing wrong here? I was not expecting an undersampled >> signal to have such poor SNR. >> >> Regards, >> >> Paul Solomon >> > > Did you find where the problem was? I'm kind of curious as to where the > source of your problems were. >
Hi, I still havnt gotten to the bottom of this one, however I have now gotten to the stage where I believe that the source of the probmen could be clock jitter on the 2s60 dev board that I am using. As I have taken the design down to just an adc and a clk and it works on my old 1s25 dev board fine but I get this probleme when run on the new 2s60 dev board. I am currently now chasing the problem up with altera. I will let you know when the issue is resolved. Regards, Paul