DAC requirement for carrier generation

Hi all,

I would like to design a digital modulator using, say, M-QAM. For speed and
simplicity, I am planning on using an FPGA development board that includes
160MSPS DACs. To avoid using extra hardware and interfacing to other boards,
I would like to generate a digital carrier in the FPGA, then convert it to
analog using the on-board DACs.

My question is a general one: How many samples per carrier cycle are
required in order to get a good analog (sinusoidal) signal at the output of
my DAC? Since I can only process the digital data at 160MSPS with my DAC, I
would be limited to a carrier frequency of 160/n MHz, where n=camples per
carrier cycle (and hence I would like to know how to choose n!).

Thanks in advance.

Snowball <sdris@softlab.ntua.gr> wrote:

> I would like to design a digital modulator using, say,
> M-QAM. For speed and simplicity, I am planning on using an FPGA
> development board that includes 160MSPS DACs. To avoid using
> extra hardware and interfacing to other boards, I would like
> to generate a digital carrier in the FPGA, then convert it to
> analog using the on-board DACs.

> My question is a general one: How many samples per carrier
> cycle are required in order to get a good analog (sinusoidal)
> signal at the output of my DAC? Since I can only process the
> digital data at 160MSPS with my DAC, I would be limited to
> a carrier frequency of 160/n MHz, where n=camples per carrier
> cycle (and hence I would like to know how to choose n!).

The answer is "it depends", and the only way to determing this
is simulation or implementation, but I've seen n as low as four work.
You will of course need a reconstruction filter after the DAC.

Incidentally, this problem comes up in what is known as
a "low IF" system.

Steve

"Snowball" <sdris@softlab.ntua.gr> wrote in message 
news:dhef1f$r2t$1@sunnews.cern.ch...
> Hi all,
>
> I would like to design a digital modulator using, say, M-QAM. For speed 
> and
> simplicity, I am planning on using an FPGA development board that includes
> 160MSPS DACs. To avoid using extra hardware and interfacing to other 
> boards,
> I would like to generate a digital carrier in the FPGA, then convert it to
> analog using the on-board DACs.
>
> My question is a general one: How many samples per carrier cycle are
> required in order to get a good analog (sinusoidal) signal at the output 
> of
> my DAC? Since I can only process the digital data at 160MSPS with my DAC, 
> I
> would be limited to a carrier frequency of 160/n MHz, where n=camples per
> carrier cycle (and hence I would like to know how to choose n!).
>
> Thanks in advance.
>
>
>
Sampling Frequency needs to be greater then the 2 * the highest frequency 
you are generating.

so for 160MSPS, the a sinusoidal would need to be < 80MHz.

if you have a modulated carrier there with a bandwidth of say 2 MHZ, then 
your fc would need to be < 79MHz so that the highest frequency is < 80MHz. 
(fc + bw/2) < fs/2

fc = center frequency
bw = bandwidth
fs = sampling frequency

cheers,

Paul Solomon 

Paul Solomon <psolomon@tpg.com.au> wrote:

>Sampling Frequency needs to be greater then the 2 * the highest frequency 
>you are generating.
>
>so for 160MSPS, the a sinusoidal would need to be < 80MHz.
>
>if you have a modulated carrier there with a bandwidth of say 2 MHZ, then 
>your fc would need to be < 79MHz so that the highest frequency is < 80MHz. 
>(fc + bw/2) < fs/2
>
>fc = center frequency
>bw = bandwidth
>fs = sampling frequency
>

Great theoretical answer.  But you'd have real trouble isolating
such a 79 MHz signal from its alias at 81 MHz.

The real question is, could you get by at Fs/3 for the center
frequency?  Or must it be lower still?

Steve

Steve Pope wrote:

>Paul Solomon <psolomon@tpg.com.au> wrote:
>
>  
>
>>Sampling Frequency needs to be greater then the 2 * the highest frequency 
>>you are generating.
>>
>>so for 160MSPS, the a sinusoidal would need to be < 80MHz.
>>
>>if you have a modulated carrier there with a bandwidth of say 2 MHZ, then 
>>your fc would need to be < 79MHz so that the highest frequency is < 80MHz. 
>>(fc + bw/2) < fs/2
>>
>>fc = center frequency
>>bw = bandwidth
>>fs = sampling frequency
>>
>>    
>>
>
>Great theoretical answer.  But you'd have real trouble isolating
>such a 79 MHz signal from its alias at 81 MHz.
>
>The real question is, could you get by at Fs/3 for the center
>frequency?  Or must it be lower still?
>
>Steve
>  
>
I'm not sure it even makes theoretical sense, considering the sinc 
rolloff that close to the end of the band (or do theoretician's DACs 
output dirac pulses :-) ).

Fs/3 can be workable, but a lot depends on the spur performance of the 
DAC, and a hundred other messy details.

Regards,
Steve

Steve Underwood  <steveu@dis.org> wrote:

>Steve Pope wrote:

>>The real question is, could you get by at Fs/3 for the center
>>frequency?  Or must it be lower still?

>I'm not sure it even makes theoretical sense, considering the sinc 
>rolloff that close to the end of the band (or do theoretician's DACs 
>output dirac pulses :-) ).

The sinc rolloff is only 3 dB at Fs/2 so it's not a deal-killer.

>Fs/3 can be workable, but a lot depends on the spur performance of the 
>DAC, and a hundred other messy details.

Yep.

S.

Steve Pope skrev:

> Steve Underwood  <steveu@dis.org> wrote:
>
> >Steve Pope wrote:
>
> >>The real question is, could you get by at Fs/3 for the center
> >>frequency?  Or must it be lower still?
>
> >I'm not sure it even makes theoretical sense, considering the sinc
> >rolloff that close to the end of the band (or do theoretician's DACs
> >output dirac pulses :-) ).
>
> The sinc rolloff is only 3 dB at Fs/2 so it's not a deal-killer.
>
> >Fs/3 can be workable, but a lot depends on the spur performance of the
> >DAC, and a hundred other messy details.
>
> Yep.
>
> S.

Analog devices has an app-note on doing an FM transmitter using a dsp
and a 125MHz DDS, its' programmed for something like 30MHz so that with
the 125MHz Fs the first alias lands and 95MHz i.e. in the normal FM
band

  
-Lasse