FIR FILTER

hi.
i have designed a FIR FILTER for 8-taps as an assignment in VHDL. i
have done the required and have almost completed with the design. i
have saved the coeff. values in the LUT ROM and i'am not very much sure
about the scaling accumulator. Scaling accu. is basically used for
round off, but these values are stored in the LUT. We give a 8 bit data
as input to the filter and addition is performed and forms a 4bit data
that is given to the LUT as the address for the coeffecients. Can any
one out here that has understood what i'am trying to explain and can
correct me and help me out by explaiing how to test my design by given
input to the filter and what values should be stored in the LUT.

Thanks 
CHEERS
AbbS

"Abbs" <abrar_ahmed_313@yahoo.co.in> wrote in message 
news:1129012775.244348.199210@g44g2000cwa.googlegroups.com...
> hi.
> i have designed a FIR FILTER for 8-taps as an assignment in VHDL. i
> have done the required and have almost completed with the design. i
> have saved the coeff. values in the LUT ROM

***That seems like a good start... but it  raises questions about the 
architecture for me.

>and i'am not very much sure
> about the scaling accumulator. Scaling accu. is basically used for
> round off, but these values are stored in the LUT. We give a 8 bit data
> as input to the filter and addition is performed and forms a 4bit data
> that is given to the LUT as the address for the coeffecients. Can any
> one out here that has understood what i'am trying to explain and can
> correct me and help me out by explaiing how to test my design by given
> input to the filter and what values should be stored in the LUT.

***Sorry, I can't follow this description.  What you need next is to get 
*input samples* from somewhere, store them somewhere and then do the 
multiply and adds.

***The scaling accumulator does the multiplies and perhaps the adds, right?

***Do you intend the architecture to store the input samples and 
subsequently compute products and sums with them (more like a programmable 
computer / DSP chip / etc?)
*or*
do you intend the architecture to stream the input data through a set of 
registers that are associated with a particular clock rate - using the 
registers as delays and sending their outputs to be multiplied by a 
particular coefficient?  That is, more of a hard-wired architecture?

Fred 

Abbs wrote:
> hi.
> i have designed a FIR FILTER for 8-taps as an assignment in VHDL. i
> have done the required and have almost completed with the design. i
> have saved the coeff. values in the LUT ROM and i'am not very much sure
> about the scaling accumulator. Scaling accu. is basically used for
> round off, but these values are stored in the LUT. We give a 8 bit data
> as input to the filter and addition is performed and forms a 4bit data
> that is given to the LUT as the address for the coeffecients. Can any
> one out here that has understood what i'am trying to explain and can
> correct me and help me out by explaiing how to test my design by given
> input to the filter and what values should be stored in the LUT.
>
> Thanks
> CHEERS
> AbbS

You should be able to address 8 taps with 3 bits.

The width of your coefficients depends on the multiply-accumulate logic
that you are using. For example, it might have two 8 bit inputs (coef
and data) and a 16 bit accumulator. After you do all eight
multiply-accumulates, you can choose to produce a result with fewer
than 16 bits by rounding. To get down to 8 bits, add 0x0080 and output
the top 8 bits.

John

hi,

www.winfilter.20m.com generates fir filter in VHDL. May you can compare
the implementation?

Adrian


Abbs wrote:
> hi.
> i have designed a FIR FILTER for 8-taps as an assignment in VHDL. i
> have done the required and have almost completed with the design. i
> have saved the coeff. values in the LUT ROM and i'am not very much sure
> about the scaling accumulator. Scaling accu. is basically used for
> round off, but these values are stored in the LUT. We give a 8 bit data
> as input to the filter and addition is performed and forms a 4bit data
> that is given to the LUT as the address for the coeffecients. Can any
> one out here that has understood what i'am trying to explain and can
> correct me and help me out by explaiing how to test my design by given
> input to the filter and what values should be stored in the LUT.
> 
> Thanks 
> CHEERS
> AbbS

Fred Marshall wrote:
> "Abbs" <abrar_ahmed_313@yahoo.co.in> wrote in message
> news:1129012775.244348.199210@g44g2000cwa.googlegroups.com...

> ***That seems like a good start... but it  raises questions about the
> architecture for me.

Abbs:
   The architecture that i have developed my code is from the pdf files
from the net. All the pdf files that i downloaded, have described the
same architecture. i'am seding along the site from which the
architecture was refered. u can just look into it if time permits and
as per my deccription given in my first post get some idea where i'am
heading and if this is the right approach. The link is given below.
please refer page no. 9. thanks too all that have replied.
Appreciated
site : http://www.altera.com/literature/an/an073.pdf

Thnaks n Regards to All
Abbs

i have implemented the FIT FILTER in 2 ways. one that i have described
in my earlier 2 posts, and the next is a simple design, to whihc i ll
paste the VHDL code.  its for a 8-tap parallel architecture. the coeff
values are taken in the ROM as constants.
can u just take a look and guide me.

thanks

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fir_filter is
    Port ( clk, reset : in std_logic;
           xin : in std_logic_vector(7 downto 0);
           yout : out std_logic_vector(15 downto 0));
end fir_filter;

architecture Behavioral of fir_filter is

signal y1, y2, y3, y4 : std_logic_vector(15 downto 0);
signal s1, s2, s3, s4 : std_logic_vector(7 downto 0);
signal r0, r1, r2, r3, r4, r5, r6, r7 : std_logic_vector(7 downto 0);
signal q : std_logic_vector(15 downto 0);
constant h0 : std_logic_vector(7 downto 0) := x"07";
constant h1 : std_logic_vector(7 downto 0) := x"0E";
constant h2 : std_logic_vector(7 downto 0) := x"12";
constant h3 : std_logic_vector(7 downto 0) := x"0E";

begin

process(clk)
begin
if (reset = '1') then
      r0 <= "00000000";
      r1 <= "00000000";
      r2 <= "00000000";
      r3 <= "00000000";
      r4 <= "00000000";
      r5 <= "00000000";
      r6 <= "00000000";
      r7 <= "00000000";

elsif (clk'event and clk = '1') then
	 r0 <= xin;
      r1 <= r0;
      r2 <= r1;
      r3 <= r2;
      r4 <= r3;
      r5 <= r4;
      r6 <= r5;
      r7 <= r6;
end if;
end process;

process(clk)
begin
if (clk'event and clk = '1') then
     s1 <= signed(r0) + signed(r7);
     s2 <= signed(r1) + signed(r6);
     s3 <= signed(r2) + signed(r5);
     s4 <= signed(r3) + signed(r4);
end if;
end process;

process(clk)
begin
if (clk'event and clk = '1') then
      y1 <= signed(s1) * signed(h0);
      y2 <= signed(s2) * signed(h1);
      y3 <= signed(s3) * signed(h2);
      y4 <= signed(s4) * signed(h3);

      q <= signed(y1) + signed(y2) + signed(y3) + signed(y4);
end if;
end process;
yout <= q;
end Behavioral;

"Abbs" <abrar_ahmed_313@yahoo.co.in> wrote in message 
news:1129538948.224981.274000@g44g2000cwa.googlegroups.com...
> Fred Marshall wrote:
>> "Abbs" <abrar_ahmed_313@yahoo.co.in> wrote in message
>> news:1129012775.244348.199210@g44g2000cwa.googlegroups.com...
>
>> ***That seems like a good start... but it  raises questions about the
>> architecture for me.
>
> Abbs:
>   The architecture that i have developed my code is from the pdf files
> from the net. All the pdf files that i downloaded, have described the
> same architecture. i'am seding along the site from which the
> architecture was refered. u can just look into it if time permits and
> as per my deccription given in my first post get some idea where i'am
> heading and if this is the right approach. The link is given below.
> please refer page no. 9. thanks too all that have replied.
> Appreciated
> site : http://www.altera.com/literature/an/an073.pdf
>
> Thnaks n Regards to All
> Abbs

Abbs,

Well, your question raises another round of questions:

- what are your design objectives?  Saving hardware?  Speed? Ease of coding 
in VHDL? (the latter isn't something I can help you with).

- why did you select the bit serial architecture?  It's slower and it's 
probably harder to think about and maybe harder to do in VHDL (I don't 
know).

- from what I see of the architecture, the LUT isn't used for the 
coefficients exactly.  Rather, it's used for storing precomputed *sums* of 
the coefficients - in all combinations that would be selected according to 
the data as input address.  Table 1, page 4.

- it appears that the scaling accumulator shifts the data one bit in order 
to keep the operands line up properly.  So, it's not "for roundoff".

I hope these observations are helpful.

Fred

Fred Marshall wrote:
> "Abbs" <abrar_ahmed_313@yahoo.co.in> wrote in message
> news:1129538948.224981.274000@g44g2000cwa.googlegroups.com...
> > Fred Marshall wrote:
> >> "Abbs" <abrar_ahmed_313@yahoo.co.in> wrote in message
> >> news:1129012775.244348.199210@g44g2000cwa.googlegroups.com...
> >
> >> ***That seems like a good start... but it  raises questions about the
> >> architecture for me.
> >
> > Abbs:
> >   The architecture that i have developed my code is from the pdf files
> > from the net. All the pdf files that i downloaded, have described the
> > same architecture. i'am seding along the site from which the
> > architecture was refered. u can just look into it if time permits and
> > as per my deccription given in my first post get some idea where i'am
> > heading and if this is the right approach. The link is given below.
> > please refer page no. 9. thanks too all that have replied.
> > Appreciated
> > site : http://www.altera.com/literature/an/an073.pdf
> >
> > Thnaks n Regards to All
> > Abbs
>
> Abbs,
>
> Well, your question raises another round of questions:
>
> - what are your design objectives?  Saving hardware?  Speed? Ease of coding
> in VHDL? (the latter isn't something I can help you with).
>
> - why did you select the bit serial architecture?  It's slower and it's
> probably harder to think about and maybe harder to do in VHDL (I don't
> know).
>
> - from what I see of the architecture, the LUT isn't used for the
> coefficients exactly.  Rather, it's used for storing precomputed *sums* of
> the coefficients - in all combinations that would be selected according to
> the data as input address.  Table 1, page 4.
>
> - it appears that the scaling accumulator shifts the data one bit in order
> to keep the operands line up properly.  So, it's not "for roundoff".
>
> I hope these observations are helpful.
>
> Fred



Thanks Fred. it was really nice to get your feedback. got to correct my
self.
About the objectives in the design, i would say.. EASY CODING IN VHDL
as of now since m just a INTERN in my company where i'am in traning so
as of now, more esential is to get and understand the algorithm.
How would i design the same for a bit-vector. I dint get any
architecture for that nor any algorithm. I would be more happier to
design an FIR filter thats more efficient. can you please send accross
any idea, any algo or hardware link across to me so i too can get an
idea about the same.
Designing an FIR filter, not the way i'am currently working on, but a
parallel bit_vector that is more fast and also saves hardware at the
same time.

AND YES FRED. U DESERVE A WHOLE LOT'S OF THANKS

U TAKE CARE SIR...

Bye

"Abbs" <abrar_ahmed_313@yahoo.co.in> wrote in message 
news:1129715307.990088.116460@z14g2000cwz.googlegroups.com...
> Fred Marshall wrote:
>> "Abbs" <abrar_ahmed_313@yahoo.co.in> wrote in message
>> news:1129538948.224981.274000@g44g2000cwa.googlegroups.com...
>> > Fred Marshall wrote:
>> >> "Abbs" <abrar_ahmed_313@yahoo.co.in> wrote in message
>> >> news:1129012775.244348.199210@g44g2000cwa.googlegroups.com...
>> >
>> >> ***That seems like a good start... but it  raises questions about the
>> >> architecture for me.
>> >
>> > Abbs:
>> >   The architecture that i have developed my code is from the pdf files
>> > from the net. All the pdf files that i downloaded, have described the
>> > same architecture. i'am seding along the site from which the
>> > architecture was refered. u can just look into it if time permits and
>> > as per my deccription given in my first post get some idea where i'am
>> > heading and if this is the right approach. The link is given below.
>> > please refer page no. 9. thanks too all that have replied.
>> > Appreciated
>> > site : http://www.altera.com/literature/an/an073.pdf
>> >
>> > Thnaks n Regards to All
>> > Abbs
>>
>> Abbs,
>>
>> Well, your question raises another round of questions:
>>
>> - what are your design objectives?  Saving hardware?  Speed? Ease of 
>> coding
>> in VHDL? (the latter isn't something I can help you with).
>>
>> - why did you select the bit serial architecture?  It's slower and it's
>> probably harder to think about and maybe harder to do in VHDL (I don't
>> know).
>>
>> - from what I see of the architecture, the LUT isn't used for the
>> coefficients exactly.  Rather, it's used for storing precomputed *sums* 
>> of
>> the coefficients - in all combinations that would be selected according 
>> to
>> the data as input address.  Table 1, page 4.
>>
>> - it appears that the scaling accumulator shifts the data one bit in 
>> order
>> to keep the operands line up properly.  So, it's not "for roundoff".
>>
>> I hope these observations are helpful.
>>
>> Fred
>
>
>
> Thanks Fred. it was really nice to get your feedback. got to correct my
> self.
> About the objectives in the design, i would say.. EASY CODING IN VHDL
> as of now since m just a INTERN in my company where i'am in traning so
> as of now, more esential is to get and understand the algorithm.
> How would i design the same for a bit-vector. I dint get any
> architecture for that nor any algorithm. I would be more happier to
> design an FIR filter thats more efficient. can you please send accross
> any idea, any algo or hardware link across to me so i too can get an
> idea about the same.
> Designing an FIR filter, not the way i'am currently working on, but a
> parallel bit_vector that is more fast and also saves hardware at the
> same time.

Abbs,

Well, I'm afraid I've run out of things to say in that regard.  I'm not an 
expert in VHDL.

The sense I get is you have a process before you that might be described in 
3 stages:

1) Decide what you need to implement - independent of implementation 
details.

2) Look at various implementations of like-machines.  Spend the time to 
understand them.  This is mostly about arithmetic, moving bits around, etc. 
It's not about signal  processing algorithms nearly so much as arithmetic.
Maybe this step includes reading VHDL for designs that are generated 
automatically as adrian suggested.

3) Having selected a likely implementation, pursue coding in VHDL.

Iterate on (2) and (3) to balance machine characteristics you'd like to have 
against your ability to get the job done in VHDL.

Fred 

 Hi John.
i need some more explanation from your side to understand this better.


> You should be able to address 8 taps with 3 bits.

 can u plzz look in this pdf doc.
 site : http://www.altera.com/literature/an/an073.pdf

 i dont understand this.  i'am giving a 8 bit input. which adds up to
give a 4 bit data that is the address to the LUT. the LUT is used for
storing precomputed *sums* of the coefficients - in all combinations
that would be selected according to the data as input address.  Table
1, page 4. in the same pdf file.


> The width of your coefficients depends on the multiply-accumulate logic
> that you are using. For example, it might have two 8 bit inputs (coef
> and data) and a 16 bit accumulator. After you do all eight
> multiply-accumulates, you can choose to produce a result with fewer
> than 16 bits by rounding. To get down to 8 bits, add 0x0080 and output
> the top 8 bits.
>
> John

you saying here that the size of the coeff is depending on the
multiply-accumulate logic, here i dont understand what you mean by
multiply-accumulate logic. is it simillar to the logic thats used in
scaling accumulator? can you please throw some light on scaling
accumulator or what you have mentioned about multiply-acc logic. where
the scalling accumulator is basically done for round off, for over
flow. multiply-acc is used to multiply the input with the coeff value.
this is one of my design that is done in the VHDL and the code is
pasted in the previous posts, in which i'am multiplying the input with
the coeff. and then taking the sum of each multiplier output, then
according to you, i have to round off by adding 0x0080 and then take
the top 8. to be very frank sir, i dint get the idea of adding 0x0080
??? y do we add this? whats the logic behind it. can you plzz explain
this idea (To get down to 8 bits, add 0x0080 ) a little more.
thanks

if u have the time can you please spare few mins looking into the pdf
file i sent and tell me what is actually stored in the LUT, is it the
same that is mentioned in Table 1, page 4. in the pdf doc. This is what
thats really bothering me, and help me get a better idea and
understanding in this design.

thanks a lot 

Abbs