"Jerry Avins" <jya@ieee.org> a �crit dans le message de news: 6Oadna83yonr8MjeRVn-ug@rcn.net...> > Clock jitter and aperture uncertainty need to be superb too. > > JerryThat was also the point I wanted to highlight when reading this thread : To get a SNR compatible with 16 bits (iI mean using actually the 16 bits, say ENOB=15, corresponding to SINAD=92dB), at 1GHz sine input (2Gsps sampling), you need a clock with an rms jitter under 3;9fs (yes, 3,9 femto-seconds, that's 10^-15). I've not done the maths to translate that into a phase noise, but I guess it will be more than challenging to find or build an oscillator like that... Friendly yours, Robert Lacoste www.alciom.com
Digitizing advice
Started by ●October 18, 2005
Reply by ●October 19, 20052005-10-19
Reply by ●October 23, 20052005-10-23
Robert Lacoste wrote:> "Jerry Avins" <jya@ieee.org> a �crit dans le message de news: > 6Oadna83yonr8MjeRVn-ug@rcn.net... > >>Clock jitter and aperture uncertainty need to be superb too. >> >>Jerry > > > That was also the point I wanted to highlight when reading this thread : To > get a SNR compatible with 16 bits (iI mean using actually the 16 bits, say > ENOB=15, corresponding to SINAD=92dB), at 1GHz sine input (2Gsps sampling), > you need a clock with an rms jitter under 3;9fs (yes, 3,9 femto-seconds, > that's 10^-15). I've not done the maths to translate that into a phase > noise, but I guess it will be more than challenging to find or build an > oscillator like that... > > Friendly yours, > Robert Lacoste > www.alciom.com > >It sounds like it may be just as hard to build an undersampling system with that kind of time accuracy as it is just to get all the samples. I'm assuming the jitter is not such a challenge if full digitizing is happening.
Reply by ●October 23, 20052005-10-23
Bryan Hackney wrote:> Robert Lacoste wrote: > >>"Jerry Avins" <jya@ieee.org> a �crit dans le message de news: >>6Oadna83yonr8MjeRVn-ug@rcn.net... >> >> >>>Clock jitter and aperture uncertainty need to be superb too. >>> >>>Jerry >> >> >>That was also the point I wanted to highlight when reading this thread : To >>get a SNR compatible with 16 bits (iI mean using actually the 16 bits, say >>ENOB=15, corresponding to SINAD=92dB), at 1GHz sine input (2Gsps sampling), >>you need a clock with an rms jitter under 3;9fs (yes, 3,9 femto-seconds, >>that's 10^-15). I've not done the maths to translate that into a phase >>noise, but I guess it will be more than challenging to find or build an >>oscillator like that... >> >>Friendly yours, >>Robert Lacoste >>www.alciom.com >> >> > > > It sounds like it may be just as hard to build an undersampling system > with that kind of time accuracy as it is just to get all the samples. > > I'm assuming the jitter is not such a challenge if full digitizing is > happening.It's the frequency of the signal and the desired precision that sets allowable jitter. Sample rate doesn't matter. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Reply by ●October 23, 20052005-10-23
Jerry Avins wrote:> Bryan Hackney wrote: >> Robert Lacoste wrote: >> >>> "Jerry Avins" <jya@ieee.org> a �crit dans le message de news: >>> 6Oadna83yonr8MjeRVn-ug@rcn.net... >>> >>> >>>> Clock jitter and aperture uncertainty need to be superb too. >>>> >>>> Jerry >>> >>> >>> That was also the point I wanted to highlight when reading this >>> thread : To get a SNR compatible with 16 bits (iI mean using actually >>> the 16 bits, say ENOB=15, corresponding to SINAD=92dB), at 1GHz sine >>> input (2Gsps sampling), you need a clock with an rms jitter under >>> 3;9fs (yes, 3,9 femto-seconds, that's 10^-15). I've not done the >>> maths to translate that into a phase noise, but I guess it will be >>> more than challenging to find or build an oscillator like that... >>> >>> Friendly yours, >>> Robert Lacoste >>> www.alciom.com >>> >>> >> >> >> It sounds like it may be just as hard to build an undersampling system >> with that kind of time accuracy as it is just to get all the samples. >> >> I'm assuming the jitter is not such a challenge if full digitizing is >> happening. > > It's the frequency of the signal and the desired precision that sets > allowable jitter. Sample rate doesn't matter. > > JerryBut of course in saying that an ADC with a higher sampling rate will normally also have a much tighter specification for it's aperture jitter. The aperture jitter as provided from the ADC supplier will be the best limit of your sampling jitter. Your sampling clock will also have jitter that will add to the aperture jitter of the ADC. Therefore the higher the input frequency the tighter must be both sampling clock and ADC aperture jitter. This means that you will want an ADC with very low aperture jitter, which is normally only found in ADCs with high sample rates. In other words, under-sampling (or bandpass sampling) is (almost) always going to trade-off device cost for noise in the sampled data. There may be ways to reduce the effective noise from the sampling jitter, but I don't know of them.
