MAC Architectures

"Jim Granville" <no.spam@designtools.co.nz> wrote in message 
news:43583dc8$1@clear.net.nz...
> langwadt@ieee.org wrote:
>> Tim Wescott skrev:
>>
>> snip
>>
>>>The original question was for an under-$2 DSP chip capable of doing
>>>audio frequency stuff, including FFTs.  I'm not the fellow who asked; it
>>>just sparked a tangential thought in my head about why there isn't some
>>>intermediate step on the way to a full-speed DSP.
>>>
>>
>>
>> I never have to buy stuff so I don't know anything about prices, but
>> philips recently announced  a couple of 70MHz ARM7TDMIs in the 2$
>> range, it's not DSPs but at 70MHz and one cycle per 8bits of
>> 32*32->64bit multiply it'll do some dsp
>
>  TI have just volume-released their 100MHz FLASH controllers, start at sub $5, 
> so not quite a $2 target, but these have FLASH(not ROM) and include 12 bit 
> 6Msps ADCs, a 150ps resolution PWM, and CAN bus
>
> 150ps PWM is a challenge even for FPGA ....
>
> http://focus.ti.com/docs/pr/pressrelease.jhtml?prelId=sc05231
>
>  The sub $2 Philips devices have quite low code sizes, but they could do some 
> 'audio frequency stuff'...

Wavefront (formerly Alesis Semiconductor) has an audio-specific DSP.  It is <$4 
for 50 MIPS.
http://www.wavefrontsemi.com/index.php?id=11,13,0,0,1,0

Also, if you open up most any DSP-based Behringer product or many of the cheap 
DSP-based stomp-boxes, you will find an obsolete 24-bit TI DSP that apparently 
was never sold in the US.  I don't know what they cost, but it must not be much 
given that a lot of that gear retails for <$100.  Unfortunately, you and I can't 
obtain those parts, AFAIK. 

The DSP is a TMS57002, which up until now is not obsolete. It's a 24
bit fixed point DSP whichis sold in the US also used by Line6, Zoom and
others. Behringer is using it on older designs but recently I saw much
of the Motorla 56364 and very powerful Shark processors in their
products. Also I heard they designed their own DSP which are used in
the current stomp boxes.

>> 150ps PWM is a challenge even for FPGA ....

Seems reasonable to me.  Use the DCM clock shifter to get a
fraction of a clock cycle.  10ns/256 is 40 ps.

I can't quite understand the fine print well enough to work out
a design on the fly.  Maybe Peter will take it as a challenge.

-- 
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"Rich Grise" <rich@example.net> wrote in message 
news:pan.2005.10.21.20.44.52.116732@example.net...
> On Wed, 19 Oct 2005 09:25:12 -0700, Tim Wescott wrote:
>
>> Jeorg's question on sci.electronics.design for an under $2 DSP chip got
>> me to thinking:
>>
>> How are 1-cycle multipliers implemented in silicon?
>
> I don't know how they do it this days, but I do know that with a
> whole shitpot load of adders, you could do it in n propagation delays,
> where n is the width of whichever operand you arrange to come in
> sideways. I almost drew a schematic. You have a set of adders as
> wide as operand "A", and its inputs are operand "A" and the "latest"
> partial product - and its outputs go to another bank of adders whose
> other inputs are either "A" again or 0, and so on - the other operand,
> "B", would be presented down the side of the array, deciding which
> partial products get added to and which don't. The LSB, of course,
> gets sent out as "product", and the carry is the MSB of the next
> partial product. They form a parallelogram.
>
> I just fired up that Xilinx S/W to see what it's got in the way of
> symbols, and it already has a 16-bit adder. With 16 of them, and 256
> AND gates, I could build a 16 x 16 multiplier that would have an
> answer in about 16 or 17 propagation delays. :-)
> <Rich fires up  Xilinx ISE...>
>
> OK, it's gonna be a day or so. Please be gentle, it's my first time. :-)
>
> Thanks!
> Rich

There is a app note


There are a few fft cores included with ise
in logicore

http://tinyurl.com/dt68x  or

<http://www.xilinx.com/xlnx/xebiz/search/searchresult.jsp?searchJSP=/xebiz/search/ipsrch.jsp&_ResultsView=Standard&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&_IPCategory=Digital+Signal+Processing&_IPSubcategory=Transform&_DeviceSupport_2022=virtex4&_DeviceSupport_1127=Spartan-3&_DeviceSupport_1128=CoolRunnerFamily&_DeviceSupport_1967=Virtex-IIProX&_DeviceSupport_1729=Spartan-II-E&_DeviceSupport_1730=XC9500Family&_DeviceSupport_1126=Virtex-IIPro&_DeviceSupport_1728=Virtex-II&_IPProducts_1129=Core&_Vendor_1=Xilinx&_SearchText=&resultNumber=All&Submit+Search.x=72&Submit+Search.y=9>

To use the builtin ones (IP cores)
new project then
add file , select IP(coregen) then wait for it to load the cores.
Then configure as required.

Depends on which chip family you have selected
to which cores are available.

Interesting to see that you can get a couple of TI dsps as
cores for fpga

http://tinyurl.com/8hojt   or

<http://www.xilinx.com/xlnx/xebiz/search/searchresult.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&category=-1211889&iLanguageID=1&_ResultsView=Standard&_IPSubcategory=DSP+Processor&_IPCategory=Digital+Signal+Processing&_IPProducts=Core>


List of xilinx app notes/white papers
http://www.xilinx.com/products/design_resources/dsp_central/resource/dsp_resources.htm


They claim a 2uS  1024 point fft
http://www.xilinx.com/prs_rls/design_win/0254altrabroadband.htm

Alex 

On Mon, 24 Oct 2005 13:41:27 +1000, Alex Gibson wrote:

[whole bunch really useful Xilinx links snipped :-) ]

Thanks! This is a keeper!

Cheers!
Rich

Bevan Weiss schrieb:
> Kolja Sulimma wrote:
> 
>> Bevan Weiss wrote:
>>
>>> Getting single cycle high speed multipliers is a very challenging
>>> prospect, and one which much research is still ongoing.
>>
>> Actually, if you cannot do full custom circuit optimizations
>> (e.g. because you do standard cell design or because you are using
>> LUTs in an FPGA) swapping wires is the only possible structural
>> optimization. All other multiplier transformations can be reduced to
>> swaps.
>>
>> An extremely nice property of swapping wires is, that it can be done
>> after placement. This is such a huge advantage that we were able to beat
>> sophisticated multiplier generators with a simple greedy algorithm when
>> applying it after placement:
>> http://eis.eit.uni-kl.de/eis/research/publications/papers/iccd04.pdf
>>
> 
> I was referring to custom design, not the use of standard cells or
> FPGAs.  It is certainly obvious that if you can't design your cells from
> scratch then you're just arranging the cells that you have available.
What is that supposed to mean?
Even if your standard cell library consists of only a NAND-gate in one
size there are still many degrees of freeedom in circuit design.
For many design problems there are architectures that trade off the
number of cells for power or speed.
Not so for single cycle multipliers. For any practicle multiplier size
the number of 1-bit adders is fixed and there exists a complete set
of transformations to automatically reach all possible setups even after
placement.


> I'm not sure if it can be reduced to swapping wires however, 
I am sure. RTFP. There is a proof in there.

though certainly in FPGAs where the entire logic design is already laid
out and
> the only configuration possible is via routing changes then this is the
> case.
This does not make the problem any easier. Well, mapping for FPGAs is
easier, but that is trivial for multipliers anyway.
For placement it does not really matter a lot what the grid is and
routing actually gets more difficult when you can only use a fixed set
of connections.

Kolja Sulimma

Kolja Sulimma wrote:
> Bevan Weiss schrieb:
>> Kolja Sulimma wrote:
>>
>>> Bevan Weiss wrote:
>>>
>>>> Getting single cycle high speed multipliers is a very challenging
>>>> prospect, and one which much research is still ongoing.
>>> Actually, if you cannot do full custom circuit optimizations
>>> (e.g. because you do standard cell design or because you are using
>>> LUTs in an FPGA) swapping wires is the only possible structural
>>> optimization. All other multiplier transformations can be reduced to
>>> swaps.
>>>
>>> An extremely nice property of swapping wires is, that it can be done
>>> after placement. This is such a huge advantage that we were able to beat
>>> sophisticated multiplier generators with a simple greedy algorithm when
>>> applying it after placement:
>>> http://eis.eit.uni-kl.de/eis/research/publications/papers/iccd04.pdf
>>>
>> I was referring to custom design, not the use of standard cells or
>> FPGAs.  It is certainly obvious that if you can't design your cells from
>> scratch then you're just arranging the cells that you have available.
 >
> What is that supposed to mean?
> Even if your standard cell library consists of only a NAND-gate in one
> size there are still many degrees of freedom in circuit design.
> For many design problems there are architectures that trade off the
> number of cells for power or speed.
> Not so for single cycle multipliers. For any practice multiplier size
> the number of 1-bit adders is fixed and there exists a complete set
> of transformations to automatically reach all possible setups even after
> placement.

So you're saying it makes no difference if booth encoding is used, or 
any form of carry ripple reduction? That it's all just a rearranging of 
wires?  Surely not, using a booth encoder requires different components 
to a simple ripple counter and so has broken that theory.

Bevan Weiss schrieb:
>> Not so for single cycle multipliers. For any practice multiplier size
>> the number of 1-bit adders is fixed and there exists a complete set
>> of transformations to automatically reach all possible setups even after
>> placement.
> 
> 
> So you're saying it makes no difference if booth encoding is used, or
> any form of carry ripple reduction? That it's all just a rearranging of
> wires?  Surely not, using a booth encoder requires different components
> to a simple ripple counter and so has broken that theory.

You are right, my definition was not exact enough. What I wrote applies
to anything that happens after partial product generation.

Carry ripple reduction does not apply to single cycle multipliers. You
need to sum up all carries at the end.
Producing a redundant number representation at the output does not
count, because now you changed the function computed by the circuit.

 Kolja Sulimma