Bhaskar Thiagarajan wrote:>"Richard Owlett" <rowlett@atlascomm.net> wrote in message >news:11pubcn12vjih5a@corp.supernews.com... > > >>Bhaskar Thiagarajan wrote: >> >> >>>"clam" <jethrolam@gmail.com> wrote in message >>>news:tK2dnfBZWp3GuQLenZ2dnUVZ_vmdnZ2d@giganews.com... >>> >>> >>> >>>>I want to sample a 1MHz RF signal at 20kHz (i.e., IF/Bandpass sampling >>>> >>>> >for > > >>>>downconversion. Is there any limiting factor on the ADC that I need to >>>>consider? e.g., does the ADC need special circuit? or small >>>>sample-and-hold delay time? >>>> >>>>CJLam >>>> >>>> >>>You need to be sure that the analog bandwidth of the ADC is higher than >>>1MHz. You should find this as a parameter in the data sheet. >>>Also, I'm assuming your BW of the RF signal is not much more than about >>>5kHz. >>> >>>Cheers >>>Bhaskar >>> >>> >>> >>> >>I assume Bhaskar means at least the sample acquisition time is less than >>.5 microsecond [ That's how I would apply Nyquist to the situation. ] >> >> > >No - as Jerry has already explained, one of the important things that >limits undersampling is the BW of the front-end of the ADC. Usually the >analog front-end of an ADC will be several tens of times (say 10x) the max >sampling rate it can support. > >It is important to take care in how you define "ADC" in this context. To so many people these days, it implies a chip, and that is how they think of an ADC. The key thing is the bandwidth up to the sampler, and the aperature of the sampler itself. These days the sampler is typically within a monolithic IC, and you cannot affect its performance. However, if you are using an ADC chip with a low performance sampler you could put a high performance external one in front of it, and get the overall result you need. In fact, you can use a super duper external sampler, and multiple slower ADCs. You pass successive narrow samples to the ADCs in turn, and combine their outputs into a final high speed sample stream. This form of polyphase sampling is much loved by those of a masochistic tendency, for the pain and misery it can cause. :-) It is a nightmare to get multiple ADCs like this to track over time and temperatures.>The sampling rate only needs to be higher than twice the BW of the signal >for satisfying Nyquist (this relates to my 5kHz remark...I used 5k and not >10k to give room for practical considerations like filter roll-off and >such). > >Cheers >Bhaskar > > > >>Given that assumption and assuming the 20kHz sampling rate is not locked >>to the 1 MHz carrier, I can not see what information could be obtained. >> >>Obviously I'm missing something. >> >>Everyone misses something, even if its only their lost youth. :-) Regards, Steve
ADC limitations for bandpass/IF sampling
Started by ●December 13, 2005
Reply by ●December 13, 20052005-12-13
Reply by ●December 13, 20052005-12-13
Bhaskar Thiagarajan wrote:>"Richard Owlett" <rowlett@atlascomm.net> wrote in message >news:11pubcn12vjih5a@corp.supernews.com... > > >>Bhaskar Thiagarajan wrote: >> >> >>>"clam" <jethrolam@gmail.com> wrote in message >>>news:tK2dnfBZWp3GuQLenZ2dnUVZ_vmdnZ2d@giganews.com... >>> >>> >>> >>>>I want to sample a 1MHz RF signal at 20kHz (i.e., IF/Bandpass sampling >>>> >>>> >for > > >>>>downconversion. Is there any limiting factor on the ADC that I need to >>>>consider? e.g., does the ADC need special circuit? or small >>>>sample-and-hold delay time? >>>> >>>>CJLam >>>> >>>> >>>You need to be sure that the analog bandwidth of the ADC is higher than >>>1MHz. You should find this as a parameter in the data sheet. >>>Also, I'm assuming your BW of the RF signal is not much more than about >>>5kHz. >>> >>>Cheers >>>Bhaskar >>> >>> >>> >>> >>I assume Bhaskar means at least the sample acquisition time is less than >>.5 microsecond [ That's how I would apply Nyquist to the situation. ] >> >> > >No - as Jerry has already explained, one of the important things that >limits undersampling is the BW of the front-end of the ADC. Usually the >analog front-end of an ADC will be several tens of times (say 10x) the max >sampling rate it can support. > >It is important to take care in how you define "ADC" in this context. To so many people these days, it implies a chip, and that is how they think of an ADC. The key thing is the bandwidth up to the sampler, and the aperature of the sampler itself. These days the sampler is typically within a monolithic IC, and you cannot affect its performance. However, if you are using an ADC chip with a low performance sampler you could put a high performance external one in front of it, and get the overall result you need. In fact, you can use a super duper external sampler, and multiple slower ADCs. You pass successive narrow samples to the ADCs in turn, and combine their outputs into a final high speed sample stream. This form of polyphase sampling is much loved by those of a masochistic tendency, for the pain and misery it can cause. :-) It is a nightmare to get multiple ADCs like this to track over time and temperatures.>The sampling rate only needs to be higher than twice the BW of the signal >for satisfying Nyquist (this relates to my 5kHz remark...I used 5k and not >10k to give room for practical considerations like filter roll-off and >such). > >Cheers >Bhaskar > > > >>Given that assumption and assuming the 20kHz sampling rate is not locked >>to the 1 MHz carrier, I can not see what information could be obtained. >> >>Obviously I'm missing something. >> >>Everyone misses something, even if its only their lost youth. :-) Regards, Steve
Reply by ●December 13, 20052005-12-13
Bhaskar Thiagarajan wrote:>"Richard Owlett" <rowlett@atlascomm.net> wrote in message >news:11pubcn12vjih5a@corp.supernews.com... > > >>Bhaskar Thiagarajan wrote: >> >> >>>"clam" <jethrolam@gmail.com> wrote in message >>>news:tK2dnfBZWp3GuQLenZ2dnUVZ_vmdnZ2d@giganews.com... >>> >>> >>> >>>>I want to sample a 1MHz RF signal at 20kHz (i.e., IF/Bandpass sampling >>>> >>>> >for > > >>>>downconversion. Is there any limiting factor on the ADC that I need to >>>>consider? e.g., does the ADC need special circuit? or small >>>>sample-and-hold delay time? >>>> >>>>CJLam >>>> >>>> >>>You need to be sure that the analog bandwidth of the ADC is higher than >>>1MHz. You should find this as a parameter in the data sheet. >>>Also, I'm assuming your BW of the RF signal is not much more than about >>>5kHz. >>> >>>Cheers >>>Bhaskar >>> >>> >>> >>> >>I assume Bhaskar means at least the sample acquisition time is less than >>.5 microsecond [ That's how I would apply Nyquist to the situation. ] >> >> > >No - as Jerry has already explained, one of the important things that >limits undersampling is the BW of the front-end of the ADC. Usually the >analog front-end of an ADC will be several tens of times (say 10x) the max >sampling rate it can support. > >It is important to take care in how you define "ADC" in this context. To so many people these days, it implies a chip, and that is how they think of an ADC. The key thing is the bandwidth up to the sampler, and the aperature of the sampler itself. These days the sampler is typically within a monolithic IC, and you cannot affect its performance. However, if you are using an ADC chip with a low performance sampler you could put a high performance external one in front of it, and get the overall result you need. In fact, you can use a super duper external sampler, and multiple slower ADCs. You pass successive narrow samples to the ADCs in turn, and combine their outputs into a final high speed sample stream. This form of polyphase sampling is much loved by those of a masochistic tendency, for the pain and misery it can cause. :-) It is a nightmare to get multiple ADCs like this to track over time and temperatures.>The sampling rate only needs to be higher than twice the BW of the signal >for satisfying Nyquist (this relates to my 5kHz remark...I used 5k and not >10k to give room for practical considerations like filter roll-off and >such). > >Cheers >Bhaskar > > > >>Given that assumption and assuming the 20kHz sampling rate is not locked >>to the 1 MHz carrier, I can not see what information could be obtained. >> >>Obviously I'm missing something. >> >>Everyone misses something, even if its only their lost youth. :-) Regards, Steve
Reply by ●December 13, 20052005-12-13
Bhaskar Thiagarajan wrote:>"Richard Owlett" <rowlett@atlascomm.net> wrote in message >news:11pubcn12vjih5a@corp.supernews.com... > > >>Bhaskar Thiagarajan wrote: >> >> >>>"clam" <jethrolam@gmail.com> wrote in message >>>news:tK2dnfBZWp3GuQLenZ2dnUVZ_vmdnZ2d@giganews.com... >>> >>> >>> >>>>I want to sample a 1MHz RF signal at 20kHz (i.e., IF/Bandpass sampling >>>> >>>> >for > > >>>>downconversion. Is there any limiting factor on the ADC that I need to >>>>consider? e.g., does the ADC need special circuit? or small >>>>sample-and-hold delay time? >>>> >>>>CJLam >>>> >>>> >>>You need to be sure that the analog bandwidth of the ADC is higher than >>>1MHz. You should find this as a parameter in the data sheet. >>>Also, I'm assuming your BW of the RF signal is not much more than about >>>5kHz. >>> >>>Cheers >>>Bhaskar >>> >>> >>> >>> >>I assume Bhaskar means at least the sample acquisition time is less than >>.5 microsecond [ That's how I would apply Nyquist to the situation. ] >> >> > >No - as Jerry has already explained, one of the important things that >limits undersampling is the BW of the front-end of the ADC. Usually the >analog front-end of an ADC will be several tens of times (say 10x) the max >sampling rate it can support. > >It is important to take care in how you define "ADC" in this context. To so many people these days, it implies a chip, and that is how they think of an ADC. The key thing is the bandwidth up to the sampler, and the aperature of the sampler itself. These days the sampler is typically within a monolithic IC, and you cannot affect its performance. However, if you are using an ADC chip with a low performance sampler you could put a high performance external one in front of it, and get the overall result you need. In fact, you can use a super duper external sampler, and multiple slower ADCs. You pass successive narrow samples to the ADCs in turn, and combine their outputs into a final high speed sample stream. This form of polyphase sampling is much loved by those of a masochistic tendency, for the pain and misery it can cause. :-) It is a nightmare to get multiple ADCs like this to track over time and temperatures.>The sampling rate only needs to be higher than twice the BW of the signal >for satisfying Nyquist (this relates to my 5kHz remark...I used 5k and not >10k to give room for practical considerations like filter roll-off and >such). > >Cheers >Bhaskar > > > >>Given that assumption and assuming the 20kHz sampling rate is not locked >>to the 1 MHz carrier, I can not see what information could be obtained. >> >>Obviously I'm missing something. >> >>Everyone misses something, even if its only their lost youth. :-) Regards, Steve
Reply by ●December 13, 20052005-12-13
Hello Bhaskar,> No - as Jerry has already explained, one of the important things that > limits undersampling is the BW of the front-end of the ADC. Usually the > analog front-end of an ADC will be several tens of times (say 10x) the max > sampling rate it can support. >If the ADC input circuitry doesn't offer such bandwidth you can sample and hold. It's really no big deal if done right. I often sample via a diode bridge driven from a toroid so that I don't have to worry about the charge injection of CMOS switches. Regards, Joerg http://www.analogconsultants.com
Reply by ●December 13, 20052005-12-13
Steve Underwood wrote: ...> Everyone misses something, even if its only their lost youth. :-)Ooh! I have to remember that one! Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Reply by ●December 14, 20052005-12-14
Hello Steve,> This form of polyphase sampling is much loved by those of a masochistic > tendency, for the pain and misery it can cause. :-) It is a nightmare to > get multiple ADCs like this to track over time and temperatures. >Nah, there are situations where you simply have to do it or else the project would die. Done it a few times. The trick is not to rely on any manual alignment whatsoever but to run a little uC alongside and then provide auto-adjust circuitry for all three variables for all ADCs minus one. Gain, offset and clock phase. It's not really rocket science. On one project they parked a big TI DSP just for that purpose. In the end its 'employment rate' hovered around a percent or two, almost idle. The cost for the analog parts and the DACs to set the trim levels was about $15 or so, peanuts compared to the cost of one of the ADCs. This was not a one-off project but it remained in production for about seven years until a faster and cheaper ADC type came out where we could get it done without multi-phase. Regards, Joerg http://www.analogconsultants.com
Reply by ●December 14, 20052005-12-14
Jerry Avins wrote:> Steve Underwood wrote: > > ... > >> Everyone misses something, even if its only their lost youth. :-) > > > Ooh! I have to remember that one! > > JerryI was wonder to what Jerry was responding so I did a Google of comp.dsp for Author=Underwood and found the relevant message. My ISP provides a Supernews account, that message does not appear. *HOWEVER* his 12/10 message "Re: Happy Hmas!" appears on Supernews, but not on Google search ;} Aside to Steve re his post Never fought battles you implied but reminded me of two aspects of "good old days" -- chopper stabilized op amps -- multi ampere ground loops in audio racks of a radio station
Reply by ●December 14, 20052005-12-14
The ADC need only be suitable for the 20 kHz sampling. But the analog hold circuit must be capable of the 1 MHz. Chris ===================== Chris Bore www.bores.com clam wrote:> I want to sample a 1MHz RF signal at 20kHz (i.e., IF/Bandpass sampling for > downconversion. Is there any limiting factor on the ADC that I need to > consider? e.g., does the ADC need special circuit? or small > sample-and-hold delay time? > > CJLam
Reply by ●December 14, 20052005-12-14
"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message news:qJ_nf.33643$q%.17135@newssvr12.news.prodigy.com...> Hello Steve, > > > This form of polyphase sampling is much loved by those of a masochistic > > tendency, for the pain and misery it can cause. :-) It is a nightmare to > > get multiple ADCs like this to track over time and temperatures. > > > > Nah, there are situations where you simply have to do it or else the > project would die. Done it a few times. > > The trick is not to rely on any manual alignment whatsoever but to run a > little uC alongside and then provide auto-adjust circuitry for all three > variables for all ADCs minus one. Gain, offset and clock phase. It's not > really rocket science. On one project they parked a big TI DSP just for > that purpose. In the end its 'employment rate' hovered around a percent > or two, almost idle. The cost for the analog parts and the DACs to set > the trim levels was about $15 or so, peanuts compared to the cost of one > of the ADCs. This was not a one-off project but it remained in > production for about seven years until a faster and cheaper ADC type > came out where we could get it done without multi-phase.Neat! I know of a few who've done this although I'm not masochistic enough (sounds like you are :-)) Sometimes there are no other options and these kinds of approaches are warranged - but in the case of the OP, I'd bet there are several viable ones. Cheers Bhaskar> Regards, Joerg > > http://www.analogconsultants.com
