Undersampling

Started by Bob Monsen January 13, 2006
I recently read an article on undersampling, and believe that I
could solve a problem I've been working on by using it. The question is
whether the solution makes sense, is a good way to proceed (there might be
much simpler solutions), and is viable.

The problem is detecting energy on a set of frequencies between 72MHz
and 73MHz, spaced at 5kHz intervals. (This is an RC broadcast detector). 

The claim in the article was that I could filter the band from 70MHz to
75MHz, and then sample the input at 10MHz. Given a 4000 sample set, I
could then determine the energy in the bands I'm interested in by doing an
FFT. The wide band is so I can use a low Q antialias filter and yet still
attenuate almost everything outside my band of interest.

I've found several ADCs that can easily handle 10MHz. A 4000 sample data
set is pretty small as far as FFTs go, I think. The amplifiers and filters
for the front end seem pretty simple. 

So

1) Will this work at all?
2) Are there other, better solutions?
3) Will the technical challenges of building this system be more than a
DSP novice can handle? I have experience with simple analog stuff, but no
real experience with fast ADCs. I would be doing the board layout and
construction. This would be a prototype.

Oh, I'd be using a dsPIC at 40 MIPS. The final question is how long a 4k
FFT will take on one of these suckers. A few times a second would probably
be adequate. 10 seconds between samples wouldn't be very useful.

Any and all help is much appreciated.

-- 
Regards,
  Bob Monsen

"I cannot persuade myself that a beneficent and omnipotent God would
have designedly created parasitic wasps with the express intention of
their feeding within the living bodies of Caterpillars"
 -- Charles Darwin

Bob Monsen wrote:

> I recently read an article on undersampling, and believe that I > could solve a problem I've been working on by using it. The question is > whether the solution makes sense, is a good way to proceed (there might be > much simpler solutions), and is viable. > > The problem is detecting energy on a set of frequencies between 72MHz > and 73MHz, spaced at 5kHz intervals. (This is an RC broadcast detector). > > The claim in the article was that I could filter the band from 70MHz to > 75MHz, and then sample the input at 10MHz. Given a 4000 sample set, I > could then determine the energy in the bands I'm interested in by doing an > FFT. The wide band is so I can use a low Q antialias filter and yet still > attenuate almost everything outside my band of interest. > > I've found several ADCs that can easily handle 10MHz. A 4000 sample data > set is pretty small as far as FFTs go, I think. The amplifiers and filters > for the front end seem pretty simple. >
You can think of downsampling as of downmixing. Your analog signal gets chopped with 10Mhz. The problems with downsampling are exactly the same as with the downmixing. Note: although the sample rate is only 10MHz, still the input of your ADC should be able to handle 70MHz analog.
> > 1) Will this work at all?
Yes, why not.
> 2) Are there other, better solutions?
There are many ICs with the direct digital downconversion, filtering and decimation. You don't have to worry about the aliasing.
> 3) Will the technical challenges of building this system be more than a > DSP novice can handle? I have experience with simple analog stuff, but no > real experience with fast ADCs. I would be doing the board layout and > construction. This would be a prototype.
It may be difficult to achieve the high performance parameters.
> Oh, I'd be using a dsPIC at 40 MIPS. The final question is how long a 4k > FFT will take on one of these suckers. A few times a second would probably > be adequate. 10 seconds between samples wouldn't be very useful.
You don't need DSP to run the FFT over 4k data several times a second. A general purpose microcontroller will do that. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
On Sat, 14 Jan 2006 01:21:15 +0000, Vladimir Vassilevsky wrote:
<sage advice>

Cool. Thanks, Vladimir. 

You mentioned IC solutions that have the downsampling built in. Do you
have any specific suggestions that you believe would be a good choice for
my problem space?

-- 
Regards,
  Bob Monsen

"Ignorance more frequently begets confidence than does knowledge: it
is those who know little, and not those who know much, who so
positively assert that this or that problem will never be solved by
science."
 -- Charles Darwin
"Bob Monsen" <rcsurname@comcast.net> wrote in message
news:pan.2006.01.14.01.00.54.819737@comcast.net...
> I recently read an article on undersampling, and believe that I > could solve a problem I've been working on by using it. The question is > whether the solution makes sense, is a good way to proceed (there might be > much simpler solutions), and is viable. > > The problem is detecting energy on a set of frequencies between 72MHz > and 73MHz, spaced at 5kHz intervals. (This is an RC broadcast detector). > > The claim in the article was that I could filter the band from 70MHz to > 75MHz, and then sample the input at 10MHz. Given a 4000 sample set, I > could then determine the energy in the bands I'm interested in by doing an > FFT. The wide band is so I can use a low Q antialias filter and yet still > attenuate almost everything outside my band of interest. > > I've found several ADCs that can easily handle 10MHz. A 4000 sample data > set is pretty small as far as FFTs go, I think. The amplifiers and filters > for the front end seem pretty simple. > > So > > 1) Will this work at all? > 2) Are there other, better solutions? > 3) Will the technical challenges of building this system be more than a > DSP novice can handle? I have experience with simple analog stuff, but no > real experience with fast ADCs. I would be doing the board layout and > construction. This would be a prototype. > > Oh, I'd be using a dsPIC at 40 MIPS. The final question is how long a 4k > FFT will take on one of these suckers. A few times a second would probably > be adequate. 10 seconds between samples wouldn't be very useful. > > Any and all help is much appreciated. > > -- > Regards, > Bob Monsen > > "I cannot persuade myself that a beneficent and omnipotent God would > have designedly created parasitic wasps with the express intention of > their feeding within the living bodies of Caterpillars" > -- Charles Darwin
Couple things to note: 1. If you want a good quality digitization you still need a very low phase jitter adc clock signal because the signal you are digitizing is changing very rapidly relative to your ADC clock. 2. FFT coding is usually very painful to do from scratch. I would make sure I had the FFT code available before I picked the chip. (Though, in your case, I'm pretty sure the dsPic code for fft is readily available.) -Clark
Bob Monsen wrote:
> [...] > The claim in the article was that I could filter the band from 70MHz to > 75MHz, and then sample the input at 10MHz. Given a 4000 sample set, I
Just as supplemental information: Shannon's theorem states that the sampling frequency has to be greater than two times the band width of the signal. (Often "band width " is confused with "maximum frequency", because if your frequency band starts at 0 Hz then the maximum frequency and the band width are the same.) So the article is right, but it is nothing new... ;-) Regards, Matthias
On Mon, 16 Jan 2006 06:22:15 -0800, Matthias wrote:

> > Bob Monsen wrote: >> [...] >> The claim in the article was that I could filter the band from 70MHz to >> 75MHz, and then sample the input at 10MHz. Given a 4000 sample set, I > > Just as supplemental information: Shannon's theorem states that the > sampling frequency has to be greater than two times the band width of > the signal. > > (Often "band width " is confused with "maximum frequency", because if > your frequency band starts at 0 Hz then the maximum frequency and the > band width are the same.) > > So the article is right, but it is nothing new... ;-) >
I wasn't familiar with the technique before. I had been considering high-Q filters, but this will be much easier. -- Regards, Bob Monsen "doing what little one can to increase the general stock of knowledge is as respectable an object of life, as one can in any likelihood pursue" -- Charles Darwin
On Sun, 15 Jan 2006 22:49:09 +0000, Anonymous wrote:

> 1. If you want a good quality digitization you still need a very low > phase jitter adc clock signal because the signal you are digitizing is > changing very rapidly relative to your ADC clock.
I was going to use a crystal oscillator running directly into the ADC. I wonder if that will provide low enough jitter? The data will be read into internal memory by the dsPIC (which has a 40MHz instruction clock, and a 'repeat' instruction.) I'm hoping it'll be fast enough to read the data in on a sample-by-sample basis, but I may have to buffer the sample set externally and read it in after the entire set is finished.
> 2. FFT coding is usually very painful to do from scratch. I would make > sure I had the FFT code available before I picked the chip. (Though, in > your case, I'm pretty sure the dsPic code for fft is readily available.)
I have a c library, which I intend to optimize for the dsPIC. The dsPIC has nice MAC instructions, which I should be able to take advantage of. Microchip has taken to charging for their DSP libraries, so I don't know if I can get their library for free. This is hardly a performance-constrained application, so a super-optimized library isn't really required. -- Regards, Bob Monsen "doing what little one can to increase the general stock of knowledge is as respectable an object of life, as one can in any likelihood pursue" -- Charles Darwin
Bob Monsen wrote:
> On Sun, 15 Jan 2006 22:49:09 +0000, Anonymous wrote: > > > 1. If you want a good quality digitization you still need a very low > > phase jitter adc clock signal because the signal you are digitizing is > > changing very rapidly relative to your ADC clock. > > I was going to use a crystal oscillator running directly into the ADC. I > wonder if that will provide low enough jitter? The data will be read into > internal memory by the dsPIC (which has a 40MHz instruction clock, and a > 'repeat' instruction.) I'm hoping it'll be fast enough to read the data in > on a sample-by-sample basis, but I may have to buffer the sample set > externally and read it in after the entire set is finished.
Or you could install a small FIFO chip between the ADC and the processor, assuming the processor can keep up on average but occasionally stalls because of disabled interrupts. Another thing to bear in mind is that you will likely want to do a series of FFTs and noncoherently combine the bin powers together. From there you will need to determine an activity threshold. One way to do that adaptively is to sort the bins into ascending order and find the percentile corresponding to the occupied bandwidth of the signal, and set the threshold a few dB higher. John