Hi all, This system consists of an DAC, a processor, and a ADC. The flow graph is like as follows: input-digital-signal -> DAC -> filter(Continuous Time) -> ADC -> output-digital-sigal The problem is that the DAC is a zero order hold, and the ADC is more strange: the ADC samples the continuous time waveform by integrate the input signal in a period T, then put that integral result as the sample at that time index. As an example, the ADC integrates the input signal from (n-0.5)T to (n+0.5)T, and then use the integration result as the output sample y[n], which is in discrete time. Now I need to formulate this system in DSP, and analyze the result, to see how much does it deviate from a second system(given the same input, how much does the output deviate, can they be made to be exactly the same output???), which is as follows: input-digital-signal -> filter(Discrete Time) -> output-digital-sigal ---------------------------- My headache is that the presence of non-traditional ADC/DAC complicated the matters... Can anybody help me? Thanks a lot!
help! how do I formulate this sampling system and analyze it?
Started by ●January 30, 2006
Reply by ●January 30, 20062006-01-30
lucy wrote:> Hi all, > > This system consists of an DAC, a processor, and a ADC. The flow graph > is like as follows: > > input-digital-signal -> DAC -> filter(Continuous Time) -> ADC -> > output-digital-sigalThat's a weird way to do things. Is it an academic exercise?> The problem is that the DAC is a zero order hold, and the ADC is more > strange: > > the ADC samples the continuous time waveform by integrate the input > signal in a period T, then put that integral result as the sample at > that time index.Most DACs have zero-order holds. A DAC must be followed by a reconstruction filter, which smooths out the steps. Your analog filter can fulfill that function while it does its other stuff. Many low-speed high precision ADCs used to be integrating types. It is usually sufficient to think of the sampling instant as the middle of the integration interval. The need to remove from the ADC input components of the signal more than half the sampling frequency makes that approximation quite accurate. The integration rejects noise frequencies that are a multiple of the sample rate. It was common practice to run these converters at the power-line frequency. That made them insensitive to line noise and its harmonics. When implemented with counters and comparators, integrating ADCs have inherent linearity. Dual and quad slope converters null out other sources of inaccuracy.> As an example, the ADC integrates the input signal from (n-0.5)T to > (n+0.5)T, and then use the integration result as the output sample > y[n], which is in discrete time. > > Now I need to formulate this system in DSP, and analyze the result, to > see how much does it deviate from a second system(given the same input, > how much does the output deviate, can they be made to be exactly the > same output???), which is as follows: > > input-digital-signal -> filter(Discrete Time) -> output-digital-sigalI don't know what filters you can use that would be identical even without complications. If you oversample sufficiently, you can come very close.> ---------------------------- > > My headache is that the presence of non-traditional ADC/DAC complicated > the matters...Your DAC is typical. How else would you have it behave? As for the ADC, remember: there are no Dirac impulses in real life. The output of every ADC or sample-and-hold represents an integration over the aperture time. Integrating converters simply extend the integration time to the full sample period. Don't sweat it. At the oversampling rate needed to match the digital and analog filters closely in overall response, the signal curvature during the sample time will be very small. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Reply by ●January 31, 20062006-01-31
Hi Jerry, Thank you for replying me. Jerry Avins wrote:> lucy wrote: > > Hi all, > > > > This system consists of an DAC, a processor, and a ADC. The flow graph > > is like as follows: > > > > input-digital-signal -> DAC -> filter(Continuous Time) -> ADC -> > > output-digital-sigal > > That's a weird way to do things. Is it an academic exercise?No, this is just some other people's paper. And I have to implement it to see its performance. I have a hard time verifying its result, because the DAC/ADC above does not generate typical math in DSP. The paper is talking about the system in terms of matlab, so actually its DAC/ADC is designed to be that, without considering the reality, (such as what you've mentioned, there is no impulse in the real world,...) I have to verify if its result is correct. But in Matlab, we have only input-digital-signal -> filter(Discrete Time) -> output-digital-sigal So the result of his paper/implementation is always different from the Matlab result. I had a hard time to decide whethat it is his system wrong, or the deviation is just because of the DAC/ADC(for example, the ADC is a integral type, instead of the sampling type, etc.) I guess I am looking for some math to analyze these types of DAC/ADC, preferrably recast the DAC/ADC into convolution, infinite sum series, and Fourier Transform domain, and see how is the result going to be different than the Matlab's discrete time implementation: input-digital-signal -> filter(Discrete Time) -> output-digital-sigal Presumably, the discrete time implement is based on the assumption of perfect DAC/ADC sampling and reconstruction... That's to say, if input-digital-signal -> DAC -> filter(Continuous Time) -> ADC -> output-digital-sigal is done with perfect DAC/ADC, I guess the result should be exactly the same as the discrete time implementation, right? Given sufficient sampling rate? --------------------------------- Now suppose my input-digital-signal is given and is a spatial waveform, I know its sampling period is 1mm per sample, and the DAC and ADC has the same period, how do I know if the sampling rate of the ADC is sufficient?
Reply by ●January 31, 20062006-01-31
lucy wrote:> Hi all,...> My headache is that the presence of non-traditional ADC/DAC complicated > the matters... > > Can anybody help me? > > Thanks a lot!Lucy, I may have misled you. If so, I'm sorry. In the spirit of not doing your homework for you, I tried to give you enough information so you could do it yourself. I threw in enough detail so that I may have obscured the issue instead of illuminating it. There is a straightforward mathematical solution to your puzzle. The integrator in the ADC acts like a filter, one that has nulls at the sampling frequency and all its harmonics. (I wrote that, but in might not have stood out.) I leave it to you to find the expression for that filter. A zero-order hold is also a filter. Since nearly all DACs have one, its effect is well documented. You will find it interesting to compare the two filters. Best of luck with this! Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Reply by ●January 31, 20062006-01-31
Jerry Avins wrote:> lucy wrote: > >> Hi all, >> >> This system consists of an DAC, a processor, and a ADC. The flow graph >> is like as follows: >> >> input-digital-signal -> DAC -> filter(Continuous Time) -> ADC -> >> output-digital-sigal > > > That's a weird way to do things. Is it an academic exercise? >-snip-> > JerryActually that's the issue I face every single time I want to model a continuous-time plant from the point of view of my digital controller. There's a pretty direct solution (see my direct reply). -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●January 31, 20062006-01-31
Tim Wescott wrote:> Jerry Avins wrote: > >> lucy wrote: >> >>> Hi all, >>> >>> This system consists of an DAC, a processor, and a ADC. The flow graph >>> is like as follows: >>> >>> input-digital-signal -> DAC -> filter(Continuous Time) -> ADC -> >>> output-digital-sigal >> >> >> >> That's a weird way to do things. Is it an academic exercise? >> > -snip- > >> >> Jerry > > > Actually that's the issue I face every single time I want to model a > continuous-time plant from the point of view of my digital controller. > There's a pretty direct solution (see my direct reply).I hadn't realized it was for a simulation only. It would be weird for a final physical realization. Did you see my having-slept-on-it reply this morning? I hope Lucy did. This is the only response from you that I see in this thread. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Reply by ●January 31, 20062006-01-31
lucy wrote:> Hi all, > > This system consists of an DAC, a processor, and a ADC. The flow graph > is like as follows: > > input-digital-signal -> DAC -> filter(Continuous Time) -> ADC -> > output-digital-sigal > > The problem is that the DAC is a zero order hold, and the ADC is more > strange: > > the ADC samples the continuous time waveform by integrate the input > signal in a period T, then put that integral result as the sample at > that time index. > > As an example, the ADC integrates the input signal from (n-0.5)T to > (n+0.5)T, and then use the integration result as the output sample > y[n], which is in discrete time. > > Now I need to formulate this system in DSP, and analyze the result, to > see how much does it deviate from a second system(given the same input, > how much does the output deviate, can they be made to be exactly the > same output???), which is as follows: > > input-digital-signal -> filter(Discrete Time) -> output-digital-sigal > > ---------------------------- > > My headache is that the presence of non-traditional ADC/DAC complicated > the matters... > > Can anybody help me? > > Thanks a lot! >You can derive an exact discrete-time model for this mixed-signal system in a fairly direct manner. You have a continuous-time filter, call it h(t), with a Laplace transform, H(s). You want to represent it with a filter in the z domain, H'(z). All you have to do is break down the system response a bit. Assuming that h(t) is a linear, time-invariant system then the whole system is a linear, shift-invariant system. This means that all you have to do is find the system impulse response from the DAC input to the ADC output and you're done. Even easier for our purposes, you just need to find the system step response and divide by z/(z-1). The DAC is a zero-order hold, so for an input step x_n that is zero for n < 0 and 1 for x >= 0 the output signal is a step x(t) that is zero for t < 0, 1 for x > 0 and is undefined (and no one cares) for x = 0. It's Laplace transform is 1/s. The output of the filter is simply Y(s) = H(s)/s. If you split the ADC up into an integrating part and a sampling part, then the integrating part is a continuous-time function who's transfer function is H_a(s) = (e^(Ts/2) - e^(-Ts/2))/s (note that H_a(s) has a finite DC gain -- you can do the math). So the input to the sampler is just Y_s(s) = (e^(Ts/2) - e^(-Ts/2))H(s)/s^2. Assuming that you define y_n as appearing at t = nT this is a non-causal system. I don't believe that, so I'm going to assume that y_1 appears at time T/2, y_2 appears at 3T/2, etc. You can modify your math to be non-causal if you feel like it, but remember to be very careful with your notation. With my change in definition Y_s(s) = (e^(-Ts/2) - e^(-3Ts/2))H(s)/s^2. At this point all you have to do is find the ramp response of the filter, probably by taking H(s)/s^2 and expanding it. Now break the pure-delay portions of Y_s into two parts: Y_s(s) = e^(-Ts/2) (1 - e^(-Ts)) H(s)/s^2. This has the Really Cool property that part of it translates straight into the z domain: 1 - e^(-Ts) <==> (z - 1) / z So you find the time-domain response of Y_s'(s) = e^(-Ts/2) H(s) / s^2 ==> y_s'(t). Now sample it at nT to get y_s'[n], and take its z transform: y_s'(nT) ==> Y_s'(z). Now recall that this is a step function, so you need to divide it by z/(z-1). Remember also you need to multiply it by (z-1)/z to take the ADC action into account that we trimmed out when we went from Y_s to Y_s': H'(z) = (z-1)^2/z^2 Y_s'(z). Ta da! This is actually easier to do if you have a state-space representation of H(s). I'm not going to work through it, I only refer you to problem 2.5-12 on page 174 of "Linear Systems" by Kailath, ISBN 0-13-536961, Library of Congress number QA402.K295. The method keeps it more in the time domain and is probably what Matlab uses. It can be easily modified for your screwy ADC (or any other screwy ADC, for that matter). -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●January 31, 20062006-01-31
Hi Tim, This is really a great method! All of a sudden I've got enlightened a lot, I feel. Thank you so much! Tim Wescott wrote:> If you split the ADC up into an integrating part and a sampling part, > then the integrating part is a continuous-time function who's transfer > function isHere is my headache part, I keep having difficulty recasting this integral type ADC into an integration part(which can be deemed as a convolutional filter), and a sampling part... In this way, I can handle this ADC in traditional way that is most commonly and thoroughly taught in DSP classes. But what should be the integration convolution kernel( the filter)? The ADC integrate the input signal against which kernel then sample?> Assuming that you define y_n as appearing at t = nT this is a non-causal > system. I don't believe that, so I'm going to assume that y_1 appears > at time T/2, y_2 appears at 3T/2, etc. You can modify your math to be > non-causal if you feel like it, but remember to be very careful with > your notation.You thought deeper than me. All I know is that in the Matlab discrete time representation, the system's prosessor/filter is centered at zero, but in Matlab representation, I have moved it to be centered at (N+1)/2, where N is the length of the filter after cutoff(the filter itself is of infinite support) and N is an odd number. So in fact, in Matlab direct implementation, the system is as simple as: digitial_spatial_waveform_signal_input => conv(input, filter), where the filter is as described above -> digital_filtered_spatial_waveform_signal_output Does this work well with your method?> Ta da!This is really cool. In fact, I am guessing that if I keep getting deviation of the paper's results from Matlab discrete-time implementation's result. I can construct an "equivalent" discrete time filter in Matlab to put in: digitial_spatial_waveform_signal_input => conv(input, filter), where the filter is as described above -> digital_filtered_spatial_waveform_signal_output and try to make their result match. Now let's think reversely, given a discrete-time filter which is used in "conv" in Matlab, how to use your above method to devise a continuous time processor/filter to put tinto the miexed signal system: digitial_spatial_waveform_signal_input => DAC (zero order hold type with no reconstruction filter) => continuous time processor/filter, but still implemented in Matlab -> ADC(integral and dump type) => digital_filtered_spatial_waveform_signal_output Theoratically, will these two discrete-time system and mixed signal system produce exactly same result? If so, how to obtain the continuous time processor from a given discrete time filter using your method? Thanks a lot!
Reply by ●January 31, 20062006-01-31
Jerry Avins wrote:> Tim Wescott wrote: > >> Jerry Avins wrote: >> >>> lucy wrote: >>> >>>> Hi all, >>>> >>>> This system consists of an DAC, a processor, and a ADC. The flow graph >>>> is like as follows: >>>> >>>> input-digital-signal -> DAC -> filter(Continuous Time) -> ADC -> >>>> output-digital-sigal >>> >>> >>> >>> >>> That's a weird way to do things. Is it an academic exercise? >>> >> -snip- >> >>> >>> Jerry >> >> >> >> Actually that's the issue I face every single time I want to model a >> continuous-time plant from the point of view of my digital controller. >> There's a pretty direct solution (see my direct reply). > > > I hadn't realized it was for a simulation only. It would be weird for a > final physical realization. Did you see my having-slept-on-it reply this > morning? I hope Lucy did. > > This is the only response from you that I see in this thread. > > JerryIt took me 30 minutes to write -- you're just too fast. Actually my favorite data acquisition system for high-performance control is to average the input for one sampling period. This puts notches at all of the harmonics of the sampling rate, so anything that might alias down into the passband of my control system gets killed dead. There's a phase penalty, but it's smaller than anything else that'll do that for me. Aside from the amount of delay (or advance) in the integrator that's pretty much what Lucy's system is doing. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●January 31, 20062006-01-31
Tim Wescott wrote: ...> Actually my favorite data acquisition system for high-performance > control is to average the input for one sampling period. This puts > notches at all of the harmonics of the sampling rate, so anything that > might alias down into the passband of my control system gets killed > dead. There's a phase penalty, but it's smaller than anything else > that'll do that for me. Aside from the amount of delay (or advance) in > the integrator that's pretty much what Lucy's system is doing.It lets the cat out of the bag, but I can't resist. That's exactly what an integrating converter does for you. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
