Re: Software PLL (SPLL)

kirgizz wrote:

> Hello board,
> 
> I'm dealing with synchronisation issue and looking for a cheap solution
> for my design. 
> 
> 
> Firstly, my external reference frequency is variable and can change, for
> example, in sweep mode (5Hz per sec). Secondly, the exact information
> about
> the ext. reference frequency is used for internal calculations in DSP (to
> generate frequency-locked quadrature sine waves).
> That's why I'd like to implenent PLL in software (like 4046 series).
> 
> I have an EZ-Kit lite DSP board from ADI with ADSP21262 onboard as basis
> (fclk=200Mhz). So I assume, it suits my design.
> 
> 
> more detailed:
> -reference signal in: TTL, 20Hz-20kHz
> -output signal: freq-locked sine waves
> -jitter (sync error): 0.01Hz (@20kHz)
> 
> I read some ebooks about PLL so I understand (theoretically) its
> functionality. Furthermore I have implemented the loop filter and the NCO
> (in place of VCO). 
> 
> My problem is the phase detector PFD. How can I program a simple and
> precise lead-lag detector? In order to avoid additional hardware I'd
> rather  use an ADC for sampling.
> 
> 
> Can you help me with an advice, please (detailed)?
> Maybe there are alternatives.
> 
> 
> Thank you in advance
> kirgizz
> 
Implementing a PLL in software uses the same basic theory as 
implementing a PLL in hardware -- you compare your synthesized signal to 
a reference, generate a phase difference, then servo the frequency of 
your synthesized signal to your reference.

Software PLLs have some significant advantages over hardware PLLs, 
mostly in the reliability of the VCO and the ability to easily concoct 
complicated loops without having it show up as an embarrassing second PC 
board.  They have some significant difficulties, as well, mostly having 
to do with the fact that you're operating in sampled time.

Most of the problems you will encounter will be because of the 
sampled-time nature of a software-based loop.

For a logic-level input signal my favorite phase detector is a timer 
capture input.  If this is available it should be able to sample the 
state of a free-running timer at the instant that the reference signal 
changes from low to high (or visa-versa).  Once this sample is taken you 
have a nice, unambiguous measure of the time that the transition 
happened to a precision proportional to the clock speed of your timer. 
You can use this time to compare to the state of your NCO phase 
accumulator (with appropriate interpolation between NCO sampling 
periods) and do whatever you want with your NCO command as a result.

If you must feed the logic-level signal into an ADC then you will run 
into severe problems with aliasing.  The sharp edges of the incoming 
signal will cause the phase measurement to be ambiguous by the ADC 
sampling interval, which will make it impossible to lock precisely.  If 
you must use the ADC input then you should use anti-alias filtering to 
soften up the edge -- which means that you should be sampling well in 
excess of your 20kHz maximum signal frequency, probably 50kHz at a 
minimum.  To determine the phase difference of your signal you just 
multiply the ADC reading by the output of your NCO and average (or 
low-pass filter) -- if you want faster lock you can get make a 
phase/frequency detector by using both the inphase and quadrature output 
of your NCO, and look at the phase rotation of the two averages (this is 
why software PLL's can be nice...).

This is more a DSP question than electronics design, so I'm taking the 
liberty of cross-posting my response to the DSP newsgroup.  Maybe 
someone there will have some good insights.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com