Software PLL (SPLL)

Hello board,

I'm dealing with synchronisation issue and looking for a cheap solution
for my design.


Firstly, my external reference frequency is variable and can change, for
example, in sweep mode (5Hz per sec). Secondly, the exact information
about the ext. reference frequency is used for internal calculations in
DSP (to generate frequency-locked inphase and quadrature sine waves).

That's why I'd like to implenent PLL in software (like 4046 series).

I have an EZ-Kit lite DSP board from ADI with ADSP21262 onboard as basis
(fclk=200Mhz). So I assume, it suits my design.


more detailed:
-reference signal in: TTL, 20Hz-20kHz
-output signal: freq-locked sine waves
-jitter (sync error): 0.01Hz (@20kHz)

I read some ebooks about PLL so I understand (theoretically) its
functionality. Furthermore I have implemented the loop filter and the NCO
(in place of VCO).

My problem is the phase detector PFD. How can I program a simple and
precise lead-lag detector? In order to avoid additional hardware I'd
rather use an ADC for sampling. As far as I know, timers from the
ADSP21262 don't have suitable capture-mode for sampling purposes.



Maybe someone have some good insights (more detailed)?


Thank you in advance
kirgizz

kirgizz wrote:
> Hello board,
>
> I'm dealing with synchronisation issue and looking for a cheap solution
> for my design.
>
>
> Firstly, my external reference frequency is variable and can change, for
> example, in sweep mode (5Hz per sec). Secondly, the exact information
> about the ext. reference frequency is used for internal calculations in
> DSP (to generate frequency-locked inphase and quadrature sine waves).
>
> That's why I'd like to implenent PLL in software (like 4046 series).
>
> I have an EZ-Kit lite DSP board from ADI with ADSP21262 onboard as basis
> (fclk=200Mhz). So I assume, it suits my design.
>
>
> more detailed:
> -reference signal in: TTL, 20Hz-20kHz
> -output signal: freq-locked sine waves
> -jitter (sync error): 0.01Hz (@20kHz)
>
> I read some ebooks about PLL so I understand (theoretically) its
> functionality. Furthermore I have implemented the loop filter and the NCO
> (in place of VCO).
>
> My problem is the phase detector PFD. How can I program a simple and
> precise lead-lag detector? In order to avoid additional hardware I'd
> rather use an ADC for sampling. As far as I know, timers from the
> ADSP21262 don't have suitable capture-mode for sampling purposes.
>
>
>
> Maybe someone have some good insights (more detailed)?
>
>
> Thank you in advance
> kirgizz

Here is psuedo code for a lead-lag filter. It is simple. Its precision
depends on the width of the accumulator, inputs, and outputs. If you
have floating point then you're home free.

coefs = [k1 k2]
lead = x * k1
acc = acc + lead
lag = acc * k2
y = lag + lead

Good luck.

John

>
>John wrote:
>
>Here is psuedo code for a lead-lag filter. It is simple. Its precision
>depends on the width of the accumulator, inputs, and outputs. If you
>have floating point then you're home free.
>
>coefs = [k1 k2]
>lead = x * k1
>acc = acc + lead
>lag = acc * k2
>y = lag + lead
>
>Good luck.
>
>John
>
>

Thank you John.

A pair of thing here are not clear to me.
What means x and why is y the sum of lag and lead?
I thought expressions would looking like this:

coefs = [k1 k2]
lead = x * k1
lag = y * k2
acc = acc + lead - lag

or 

coeff = kd
acc = acc + lead - lag
vd = kd*acc

Have you programmed such software PLL? It's very interesting how do you
get your x there? I mean the way you acquire the input square wave (by ADC
or Timer). What did you use?



regards,
kirgizz

kirgizz wrote:
> >
> >John wrote:
> >
> >Here is psuedo code for a lead-lag filter. It is simple. Its precision
> >depends on the width of the accumulator, inputs, and outputs. If you
> >have floating point then you're home free.
> >
> >coefs = [k1 k2]
> >lead = x * k1
> >acc = acc + lead
> >lag = acc * k2
> >y = lag + lead
> >
> >Good luck.
> >
> >John
> >
> >
>
> Thank you John.
>
> A pair of thing here are not clear to me.
> What means x and why is y the sum of lag and lead?
> I thought expressions would looking like this:
>
> coefs = [k1 k2]
> lead = x * k1
> lag = y * k2
> acc = acc + lead - lag
>
> or
>
> coeff = kd
> acc = acc + lead - lag
> vd = kd*acc
>
> Have you programmed such software PLL? It's very interesting how do you
> get your x there? I mean the way you acquire the input square wave (by ADC
> or Timer). What did you use?
>
>
>
> regards,
> kirgizz


Yes, I've programmed them. x is typically the phase error. It comes
from a phase detector. There are quite a view different types. One is a
zero crossing detector, in which the phase error is the value of high
speed (compared to the input) counter at the time of the crossing.

JS

>
>John wrote:
>
>Yes, I've programmed them. x is typically the phase error. It comes
>from a phase detector. There are quite a view different types. One is a
>zero crossing detector, in which the phase error is the value of high
>speed (compared to the input) counter at the time of the crossing.
>
>JS
>
>

Do you mean by that you're using an external phase detector and feeding
the "error-impulses" into your DSP/uC? You implement the loop in program
and send the NCO output to this external phase detector? Do you?

regards,
 kirgizz