Is it possible to have parallel cycling system? In this a billion channels could each have a 1 Hz clock. The goal is to gain a clock rate of 1 GHz by supplying each of those billion channels with a 1 Hz clock. Each cycle per second has its own channel. 1 Hz = 1 channel. 1 GHz = 1 billion channels. This is called "parallel clocking". One big advantage I see with this is less heat generated with the same clock speed. NOTE: *Hz* is different from *bits* and thus they are not to be confused with each other.
Parallel Clock Cycles?
Started by ●July 10, 2004
Reply by ●July 10, 20042004-07-10
"Curious" <curious11112001@yahoo.com> wrote in message news:34a4f456.0407101311.59dc261d@posting.google.com...> Is it possible to have parallel cycling system? In this a billion > channels could each have a 1 Hz clock. The goal is to gain a clock > rate of 1 GHz by supplying each of those billion channels with a 1 Hz > clock. Each cycle per second has its own channel. 1 Hz = 1 channel. 1 > GHz = 1 billion channels. This is called "parallel clocking". One big > advantage I see with this is less heat generated with the same clock > speed. >Sure. But there could be any number of practical problems including real estate for a billion channels. Also, one must ask why you'd want to have 1 billion clock phases? What would be the purpose? How would you tell them apart? Would you need to? etc. etc..... I really don't think it makes sense to talk about it. I've been proven to be misguided on any number of occasions.... What are you trying to accomnplish exactly? Fred
Reply by ●July 11, 20042004-07-11
On Sat, 10 Jul 2004 17:39:09 -0700, "Fred Marshall" <fmarshallx@remove_the_x.acm.org> wrote:> >"Curious" <curious11112001@yahoo.com> wrote in message >news:34a4f456.0407101311.59dc261d@posting.google.com... >> Is it possible to have parallel cycling system?Yes.>> In this a billion >> channels could each have a 1 Hz clock. The goal is to gain a clock >> rate of 1 GHz by supplying each of those billion channels with a 1 Hz >> clock. Each cycle per second has its own channel. 1 Hz = 1 channel. 1 >> GHz = 1 billion channels. This is called "parallel clocking". One big >> advantage I see with this is less heat generated with the same clock >> speed.The heat generated (in modern CMOS logic) is proportional to the clock rate, but down at 1 Hz the leakage current may dominate. You generally get the most computation per energy expended by running a CPU (or other logic block) at full speed. Look at it this way - a billion processors each running a 1GHz (using the assumption that one operation is done in one clock cycle, but this works for getting the approximate order of magnitude) will do a total of 10^18 operations per second. That would be enough to get the attention of quite a few US Government agencies...>Sure. But there could be any number of practical problems including real >estate for a billion channels.Last I heard (which may have been years ago) they are approaching a billion transistors on the lastest high-end CPU chips, that would be enough for an inverter for each channel. That doesn't seem useful - maybe when you can do an FFT on a billion points...>Also, one must ask why you'd want to have 1 >billion clock phases? What would be the purpose? How would you tell them >apart? Would you need to? etc. etc..... > >I really don't think it makes sense to talk about it. I've been proven to >be misguided on any number of occasions....Having a billion phases is a bit over-the-top, but I recall a description of a core memory for a fast (at the time) computer that used a phased memory. Core memory generally has an access time of one microsecond. This memory was set up to each consecutive location was on a different plane of the memory, so that when reading consecutive memory locations they arrived at 1/8th of a microsecond intervals. Of course the total bandwidth on average wasn't 8 times that of regular memory because all accesses aren't sequential, but it was substantially faster.>What are you trying to accomnplish exactly?It looks like a "theoretical question" to me.>Fred
Reply by ●July 11, 20042004-07-11
Curious wrote:> Is it possible to have parallel cycling system? In this a billion > channels could each have a 1 Hz clock. The goal is to gain a clock > rate of 1 GHz by supplying each of those billion channels with a 1 Hz > clock. Each cycle per second has its own channel. 1 Hz = 1 channel. 1 > GHz = 1 billion channels. This is called "parallel clocking". One big > advantage I see with this is less heat generated with the same clock > speed. > > NOTE: *Hz* is different from *bits* and thus they are not to be > confused with each other.It is already done, usually once you have everything running as screamingly fast as possible and you still need more speed. One example is the "pipelining" that processors do -- generally you'll have a pipeline stage that fetches an instruction, one that decodes, one that computes, one that saves, etc. Generally the pipeline will run at one instruction per clock tick but it will take more than one clock tick for each instruction to complete. Also generally, the pipeline will meet certain instructions that make it "stall", i.e. a conditional branch where the wrong instruction was fetched. Things are fancy these days, so processors will often have eight or more pipeline stages, and will reorder the execution of instructions within the pipeline to make things faster. Parallel algorithms generally only work where the problem has some inherent parallel structure to it, and to really gain the speed improvement the hardware needs to reflect the algorithm. So you could make a _really fast_ FFT by having each stage of you algorithm do N/2 butterfly calculations; you'd have N multipliers, N adders, and N W terms, and it would take log_2(N) steps to do it. You could increase the throughput by having log_2(N) stages, so you could feed a new FFT source data at each clock tick. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●July 11, 20042004-07-11
Ben Bradley <ben_nospam_bradley@mindspring.com> wrote in message news:<s7j1f0t3aud403odvivqigr5h2o9mnk6mn@4ax.com>...> On Sat, 10 Jul 2004 17:39:09 -0700, "Fred Marshall" > <fmarshallx@remove_the_x.acm.org> wrote: > > > > >"Curious" <curious11112001@yahoo.com> wrote in message > >news:34a4f456.0407101311.59dc261d@posting.google.com... > >> Is it possible to have parallel cycling system? > > Yes. > > >> In this a billion > >> channels could each have a 1 Hz clock. The goal is to gain a clock > >> rate of 1 GHz by supplying each of those billion channels with a 1 Hz > >> clock. Each cycle per second has its own channel. 1 Hz = 1 channel. 1 > >> GHz = 1 billion channels. This is called "parallel clocking". One big > >> advantage I see with this is less heat generated with the same clock > >> speed. > > The heat generated (in modern CMOS logic) is proportional to the > clock rate, but down at 1 Hz the leakage current may dominate. You > generally get the most computation per energy expended by running a > CPU (or other logic block) at full speed. > Look at it this way - a billion processors each running a 1GHz > (using the assumption that one operation is done in one clock cycle, > but this works for getting the approximate order of magnitude) will do > a total of 10^18 operations per second. That would be enough to get > the attention of quite a few US Government agencies... > > >Sure. But there could be any number of practical problems including real > >estate for a billion channels. > > Last I heard (which may have been years ago) they are approaching a > billion transistors on the lastest high-end CPU chips, that would be > enough for an inverter for each channel. That doesn't seem useful - > maybe when you can do an FFT on a billion points... > > >Also, one must ask why you'd want to have 1 > >billion clock phases? What would be the purpose? How would you tell them > >apart? Would you need to? etc. etc..... > > > >I really don't think it makes sense to talk about it. I've been proven to > >be misguided on any number of occasions.... > > Having a billion phases is a bit over-the-top, but I recall a > description of a core memory for a fast (at the time) computer that > used a phased memory. Core memory generally has an access time of one > microsecond. This memory was set up to each consecutive location was > on a different plane of the memory, so that when reading consecutive > memory locations they arrived at 1/8th of a microsecond intervals. Of > course the total bandwidth on average wasn't 8 times that of regular > memory because all accesses aren't sequential, but it was > substantially faster.If only all algorithms could be "non-sequentialized" :-)> >What are you trying to accomnplish exactly? > > It looks like a "theoretical question" to me.Yes. The purpose of this "parallel Hz" is to result in a fast clock rate but at the same time decrease the strain on the clock. For this, their are the same number of channels for each Hz. 1 Hz = 1 channel. 1 GHz = 1 billion channels.
Reply by ●July 11, 20042004-07-11
Tim Wescott <tim@wescottnospamdesign.com> wrote in message news:<10f3373sq04ml74@corp.supernews.com>...> Parallel algorithms generally only work where the problem has some > inherent parallel structure to it, and to really gain the speed > improvement the hardware needs to reflect the algorithm. > So you could > make a _really fast_ FFT by having each stage of you algorithm do N/2 > butterfly calculations; you'd have N multipliers, N adders, and N W > terms, and it would take log_2(N) steps to do it.> You could increase > the throughput by having log_2(N) stages, so you could feed a new FFT > source data at each clock tick.What you're describing is parallel "bits" not parallel "hz". My goal is to somehow gain a clock rate of n ticks/second by giving n channels each 1 tick/second.
Reply by ●July 11, 20042004-07-11
Ben Bradley <ben_nospam_bradley@mindspring.com> wrote in message news:<s7j1f0t3aud403odvivqigr5h2o9mnk6mn@4ax.com>...> Look at it this way - a billion processors each running a 1GHzWhat I was proposing is a billion channels each containing 1 clock. Each of these clocks work at 1 Hz frequency. The end result should somehow be a clock rate of 1 GHz when all channels are being used. This is different from bits per cycle.
Reply by ●July 11, 20042004-07-11
Curious wrote: ...> Yes. The purpose of this "parallel Hz" is to result in a fast clock > rate but at the same time decrease the strain on the clock. For this, > their are the same number of channels for each Hz. 1 Hz = 1 channel. 1 > GHz = 1 billion channels.What do you mean by "strain on the clock"? Suppose you want to add two numbers, or send out a serial character. How would that work? Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Reply by ●July 12, 20042004-07-12
On Sun, 11 Jul 2004 01:35:32 -0400, Ben Bradley <ben_nospam_bradley@mindspring.com> wrote:>On Sat, 10 Jul 2004 17:39:09 -0700, "Fred Marshall" ><fmarshallx@remove_the_x.acm.org> wrote: > >> >>"Curious" <curious11112001@yahoo.com> wrote in message >>news:34a4f456.0407101311.59dc261d@posting.google.com... >>> Is it possible to have parallel cycling system? > > Yes. > >>> In this a billion >>> channels could each have a 1 Hz clock. The goal is to gain a clock >>> rate of 1 GHz by supplying each of those billion channels with a 1 Hz >>> clock. Each cycle per second has its own channel. 1 Hz = 1 channel. 1 >>> GHz = 1 billion channels. This is called "parallel clocking". One big >>> advantage I see with this is less heat generated with the same clock >>> speed. > > The heat generated (in modern CMOS logic) is proportional to the >clock rate, but down at 1 Hz the leakage current may dominate. You >generally get the most computation per energy expended by running a >CPU (or other logic block) at full speed.I think for modern CMOS logic (e.g. 0.1something micron), the leakage current will dominate even if the clock is well above 1MHz. Regards, Allan.
Reply by ●July 12, 20042004-07-12
Curious wrote:> What you're describing is parallel "bits" not parallel "hz". My goal > is to somehow gain a clock rate of n ticks/second by giving n channels > each 1 tick/second.Yes, that is rock solid arithmetic. Bob -- "Things should be described as simply as possible, but no simpler." A. Einstein
