I just find that the FLASH is 4M and it has 22 add lines. The add lines[0:18] are connected to the DM642 directly, while [19:21] are connected to FPGA. I guess that they use the FPGA as a address decoder to implement paging. However, I don't know how it decode. I mean that what the logic is. Are there any other pin of EMIF connected to the FPGA and used in the decode logic?
how to extend the address bus of the onboard FLASH(4M) of EVM_DM642
Started by ●April 17, 2006