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A/D Buffering on the TI TMS320F2812

Started by Randy Yates April 22, 2006
Hi Folks,

The 2812 has an on-board A/D converter, but it appears there
is no DMA engine on this machine. Thus it appears that the
buffering of samples from the A/D to internal memory must
be performed on a sample-by-sample basis.

Since this converter can operate as high as 12.5 MHz, this
seems like it's going to eat 12.5 MIPS at a minimum just
for this function at this A/D rate.

Am I wrong? Am I missing something in this machine's
architecture?

--Randy

Randy Yates wrote:

> Hi Folks, > > The 2812 has an on-board A/D converter, but it appears there > is no DMA engine on this machine. Thus it appears that the > buffering of samples from the A/D to internal memory must > be performed on a sample-by-sample basis. > > Since this converter can operate as high as 12.5 MHz, this > seems like it's going to eat 12.5 MIPS at a minimum just > for this function at this A/D rate. > > Am I wrong? Am I missing something in this machine's > architecture? > > --Randy >
IIRC it does have a 16-deep FIFO, which you can transfer out into regular RAM at 1-per-clock. I've used it to sample two channels at 80kHz, filter, decimate to 10kHz and run a fairly complex controller (two PI controllers, each with a notch and a low pass, so eight states in all). The processor has to work hard, but does it just fine. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/
Hi Tim,

I scanned the documents quickly, but I think you're correct. There are
16 registers that can be used like a FIFO. However, so what? As you
say, it still takes 1 clock per sample to transfer them to RAM, so
whether you take 16 clocks every 16/Fs, or 1 clock every 1/Fs,
what's the difference?

At your rates it's not a problem. But we're planning on running this
at up to 5.12 MHz in simultaneous capture mode, so we'd be shoving
10+ MIPS down the toilet.

I feel like kicking TI's butt for not putting a DMA controller on this
machine.

--RY

Randy Yates wrote:

> Hi Tim, > > I scanned the documents quickly, but I think you're correct. There are > 16 registers that can be used like a FIFO. However, so what? As you > say, it still takes 1 clock per sample to transfer them to RAM, so > whether you take 16 clocks every 16/Fs, or 1 clock every 1/Fs, > what's the difference? > > At your rates it's not a problem. But we're planning on running this > at up to 5.12 MHz in simultaneous capture mode, so we'd be shoving > 10+ MIPS down the toilet. > > I feel like kicking TI's butt for not putting a DMA controller on this > machine. > > --RY >
Are you controlling a three phase motor with it? If not, you're not in the target market for the part. It would be nice to have a part with that core and a DMA engine on the ADC -- but that would take more silicon, and make it cost more, so I would have liked it less for my application. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/
Un bel giorno Randy Yates digit�:

> I scanned the documents quickly, but I think you're correct. There are > 16 registers that can be used like a FIFO. However, so what? As you > say, it still takes 1 clock per sample to transfer them to RAM, so > whether you take 16 clocks every 16/Fs, or 1 clock every 1/Fs, > what's the difference?
If you had DMA, what would have been the difference? After all, you have to access the stored data at a certain moment. I suppose that in most applications for this processor (which is more a powerful microcontroller rather than a number crunching DSP) the ADC data has to be processed in realtime and sample-by-sample, for example to feed a FIR filter or something like that. -- asd
Randy Yates wrote:
> Hi Tim, > > I scanned the documents quickly, but I think you're correct. There are > 16 registers that can be used like a FIFO. However, so what? As you > say, it still takes 1 clock per sample to transfer them to RAM, so > whether you take 16 clocks every 16/Fs, or 1 clock every 1/Fs, > what's the difference?
Would you rather service an interrupt every sample, or every 16 samples? ...
> I feel like kicking TI's butt for not putting a DMA controller on this > machine.
It is probably intended for an application that wouldn't profit from one. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
The difference is that the samples wouldn't have
to be transferred by the processor. 

--RY

No, I'm not. Good point.

--RY

> Would you rather service an interrupt every sample, or every 16 samples?
Um, yes, true. I guess I'm not used to bit-banging like this since the early 80's. So the choice is between M*F MIPS or F MIPS, where F is the sample rate and M is some integer representing the interrupt overhead. Yeah, sure I'd choose F MIPS, but that's still horrible! --RY
> It would be nice to have a part with that core and a DMA engine on the > ADC -- but that would take more silicon, and make it cost more, so I > would have liked it less for my application.
Actually, wait a darn minute here. I found yesterday a stripped-down 5501 at 300 MHz for $5. The 2812 is around $15. So tell me why the 2812 is so cheap? Yes, it's got integrated FLASH and A/D, but still ... --RY