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McBsp Problems

Started by lazarman June 5, 2006
hi

We are using the McBSP module to communicate to an FPGA 

To simulate this I will use 2 2812 DSK's constraints are External clock
coming from FPGA is 4MHz. The hardware initialization capability shall
initialize the McBSP module of the DSP to receive in slave mode and
transmit in master mode.On transmitting/receiving MSb is shifted out/in
from the FIFO�s which is the default McBSP setting The design constraints
are 1) Transmission master, FIFO, 16-bit words, no interrupts, and
external clock; 2) Receiving - slave, FIFO, 32 bit words, no interrupts,
external clock. 3) FS signal is active High for MSb of each message and is
coincident with the first data bit (i.e. RDATDLY and XDATDLY are 0) 4) FIFO
limits: receiving 7 32-bit words sending 12 16-bit words It is unclear what
value to put in bit FIELD FPER of McBsp Rewgister SRGR2 to generate a frame
sync period]

Have had no luck seeing any received data in FIFO

Any help appreciated

Settings are
// sender


#include "hw_mcbsp.h"
#include "dsp2812_mcbsp.h"
// Define the level of the FIFO 1-16
#define FIFO_LEVEL 7
#define WORD_SIZE 32        // Run atest in 32-bit mode 

// Prototype statements for functions found within this file.

// Global data for this example
unsigned int sdata1 = 0x000;    // Sent Data
unsigned int rdata1 = 0x000;    // Recieved Data

unsigned int sdata2 = 0x000;    // Sent Data
unsigned int rdata2 = 0x000;    // Recieved Data

unsigned int rdata1_point;
unsigned int rdata2_point;

unsigned int DCEMsg[16] =
{0xE787,0,0x8000,0,0,0,0xC865,0,0,0,0,0,0,0,0xAAAA,0xAAAA};

void  InitializeDCEMCBSP(void)
{

   unsigned int i;

     McbspaRegs.MFFTX.all=0x0000;
    
    // McBSP FIFO recieve register bit definitions:
    
    McbspaRegs.MFFRX.all=0x001F;
    
// McBSP FIFO control register bit definitions:


    McbspaRegs.MFFCT.all=0x0;
    
    McbspaRegs.MFFINT.all=0x0;
    McbspaRegs.MFFST.all=0x0;  
    McbspaRegs.MFFTX.bit.MFFENA=1;         // Enable FIFO
    McbspaRegs.MFFTX.bit.TXFIFO_RESET=1;  // Enable Transmit channel
    McbspaRegs.MFFRX.bit.RXFIFO_RESET=1;  // Enable Receive channel
 
	// SPCR2 control register bit definitions:

    McbspaRegs.SPCR2.all=0x0000;
    
// SPCR1 control register bit definitions:

#ifdef LOOP_BACK
    McbspaRegs.SPCR1.bit.DLB =1;     //loopback
#endif

  McbspaRegs.SPCR1.bit.CLKSTP =2;     //Clock starts with rising edge
  
// RCR2 control register bit definitions:

    McbspaRegs.RCR2.all=0x0;
    McbspaRegs.RCR2.bit.RFIG = 1;				  // Ignore extra FS
    

	McbspaRegs.RCR2.bit.RFRLEN2=0x6;  // recieve 7 words


	McbspaRegs.XCR2.all=0x02;             // Ignore Extra Tx Sync Pulse
	McbspaRegs.XCR2.bit.XRFRLEN2 = 11;     //12 16 bit words in frame	
// SRGR1 control register bit definitions:
	
// PCR control register bit definitions:

	
    McbspaRegs.XCR2.all=0x02;             // Ignore Extra Tx Sync Pulse
    McbspaRegs.XCR1.all=0x0;
    // SRGR2 Sample rate generator control register bit definitions:
    McbspaRegs.SRGR2.all=0x2000; 
    McbspaRegs.SRGR2.bit.FPER = 800;  //FS every 2 mSec  
    McbspaRegs.SRGR2.bit.CLKSM = 1;                  
    McbspaRegs.MCR2.all=0x0;
    McbspaRegs.MCR1.all=0x0;

    McbspaRegs.PCR.bit.CLKRM = 1;  //1 CLKR is an output pin and is driven

    							   // by the internal sample rate generator.
     McbspaRegs.PCR.bit.CLKXM = 1; //1 CLK(R/X) is an output pin and is
driven 
     							   //by the internal sample rate generator.
     McbspaRegs.PCR.bit.FSXM = 1;  //Frame synchronization generated
internally by sample rate generator. FSR is
								  // an output pin except when GSYNC = 1 in SRGR.
 
     McbspaRegs.SRGR1.bit.CLKGDV = 80; // .375 MHz   
 

    McbspaRegs.RCR1.bit.RWDLEN1=5;     // 32-bit word
    McbspaRegs.XCR1.bit.XWDLEN1=5;     // 32-bit word
    McbspaRegs.XCR1.bit.XFRLEN1 = 7;   // tx 8 32 bit words
   
     McbspaRegs.SPCR2.bit.XRST =1;      // enable XRST/RRST
    McbspaRegs.SPCR1.bit.RRST=1;
    delay_loop();   
    McbspaRegs.SPCR2.all |=0x00C0;     // Only enable FRST,GRST used after

    
   }

// Step 5. User specific code,

  void test_DCE_mcbsp(void)
{
int i;

             for(i = 0; i < FIFO_LEVEL; i++)
             {
 
                    DCE_mcbsp_xmit(DCEMsg[(i*2)+1],DCEMsg[i*2]);
                     
             }

}     

// Some Useful local functions
void delay_loop()
{
    long      i;
    for (i = 0; i < 1000000; i++) {}
}






void DCE_mcbsp_xmit(int a, int b)
{
    McbspaRegs.DXR2.all=b;
    McbspaRegs.DXR1.all=a;
}



// TITLE:	DSP281x CE Receiver McBSP Simulator program. 
//

#include "hw_mcbsp.h"
#include "dsp2812_mcbsp.h"
// Define the level of the FIFO 1-16
#define FIFO_LEVEL 8
#define WORD_SIZE 32        // Run a loopback test in 32-bit mode 

// Prototype statements for functions found within this file.
void init_mcbsp_32bit(void);
void CE_mcbsp_xmit(int a, int b);
void test_mcbsp(void);
void init_mcbsp_dcebit();

// Global data for this example

unsigned int CEMsg[16] =
{0xE787,0,0x8000,0,0,0,0xC865,0,0,0,0,0,0,0,0xAAAA,0xAAAA};

void  InitializeCEMCBSP(void)
{

   unsigned int i;
  
   GpioMuxRegs.GPFMUX.all=0x3f3f;    // Select GPIOs to be McBSP pins  
    McbspaRegs.MFFTX.all=0x0000;
    
    // McBSP FIFO recieve register bit definitions:
    McbspaRegs.MFFRX.all=0x001F;
    
// McBSP FIFO control register bit definitions:
 
    McbspaRegs.MFFCT.all=0x0;
    
    McbspaRegs.MFFINT.all=0x0;
    McbspaRegs.MFFST.all=0x0;  
    McbspaRegs.MFFTX.bit.MFFENA=1;         // Enable FIFO
    McbspaRegs.MFFTX.bit.TXFIFO_RESET=1;  // Enable Transmit channel
    McbspaRegs.MFFRX.bit.RXFIFO_RESET=1;  // Enable Receive channel
    McbspaRegs.SPCR2.all=0x0000;
    
// SPCR1 control register bit definitions:

#ifdef LOOP_BACK
    McbspaRegs.SPCR1.bit.DLB =1;     //loopback
#endif

  McbspaRegs.SPCR1.bit.CLKSTP =2;     //Clock starts with rising edge
// RCR2 control register bit definitions:
    McbspaRegs.RCR2.all=0x0;
    
//    McbspaRegs.RCR1.all=0x0;
	McbspaRegs.RCR2.bit.RFRLEN2=0x6;  // recieve 7 words
	McbspaRegs.RCR2.bit.RFIG = 1;	// Ignore extra FS
	McbspaRegs.XCR2.all=0x02;             // Ignore Extra Tx Sync Pulse
	McbspaRegs.XCR2.bit.XRFRLEN2 = 11;     //12 16 bit words in frame	
// SRGR1 control register bit definitions:
    McbspaRegs.XCR2.all=0x02;             // Ignore Extra Tx Sync Pulse
    McbspaRegs.XCR1.all=0x0;
    McbspaRegs.SRGR2.all=0x2000; 
    McbspaRegs.SRGR2.bit.FPER = 800;  //FS every 2 mSec                   

    McbspaRegs.SRGR2.bit.CLKSM = 1;                  
    McbspaRegs.MCR2.all=0x0;
    McbspaRegs.MCR1.all=0x0;
    McbspaRegs.PCR.all=0x00a00;
     McbspaRegs.SRGR1.bit.CLKGDV = 80; // .375 MHz   
     McbspaRegs.RCR1.bit.RWDLEN1=5;     // 32-bit word
    McbspaRegs.XCR1.bit.XWDLEN1=5;     // 32-bit word
    McbspaRegs.XCR1.bit.XFRLEN1 = 7;   // tx 8 32 bit word   
 
           
    //  McBSP Reset to enable 
    McbspaRegs.SPCR2.bit.XRST =1;      // enable XRST/RRST
    McbspaRegs.SPCR1.bit.RRST=1;
    delay_loop();   
    McbspaRegs.SPCR2.all |=0x00C0;     // Only enable FRST,GRST used after

    
   }

// Step 5. User specific code,
void test_CE_mcbsp(void)
{
int i;

             for(i = 0; i < FIFO_LEVEL; i++)
             {
 
                    CE_mcbsp_xmit(CEMsg[(i*2)+1],CEMsg[i*2]);
                     
             }

}     

void CE_mcbsp_xmit(int a, int b)
{
    McbspaRegs.DXR2.all=b;
    McbspaRegs.DXR1.all=a;
}