For 1 instruction / nanosecond ( plus a nanosecond for on-chip ram access,) So far my possible architecture list includes, 1) A general purpose architecture, http://groups.google.com/group/comp.lang.java.machine/browse_frm/thread/a942766d2ab96799/b400d03ddc0f5a4f 2) An embedded appliance architecture, http://www.elecdesign.com/Articles/Print.cfm?AD=1&ArticleID=12692 Do you have more links to other websites? Thanks, anon
1 instruction / nanosecond plus a nanosecond for on-chip cache access,
Started by ●July 6, 2006
Reply by ●July 7, 20062006-07-07
In comp.arch anon <cpu16x1832@wmconnect.com> wrote:> For 1 instruction / nanosecond ( plus a nanosecond for on-chip ram > access,)[...] I'm not sure whether you know this, but even several 5 year old GP chips with clocks of 1 GHz (i.e. 1 ns cycle time for the pipelines) can perform several (e.g. upto 10) operations in the 1 clock cycle -- even 1 to 4 double precision fp ops.
Reply by ●July 7, 20062006-07-07
russell kym horsell wrote:> In comp.arch anon <cpu16x1832@wmconnect.com> wrote: > > For 1 instruction / nanosecond ( plus a nanosecond for on-chip ram > > access,) > [...] > > > I'm not sure whether you know this, but even several 5 year old GP chips with > clocks of 1 GHz (i.e. 1 ns cycle time for the pipelines) can > perform several (e.g. upto 10) operations in the 1 clock cycle -- even 1 to 4 > double precision fp ops.Plus fabrication technology, ... Website(s) please.
Reply by ●July 7, 20062006-07-07
russell kym horsell wrote:> In comp.arch anon <cpu16x1832@wmconnect.com> wrote: > > For 1 instruction / nanosecond ( plus a nanosecond for on-chip ram > > access,) > [...] > > > I'm not sure whether you know this, but even several 5 year old GP chips with > clocks of 1 GHz (i.e. 1 ns cycle time for the pipelines) can > perform several (e.g. upto 10) operations in the 1 clock cycle -- even 1 to 4 > double precision fp ops.Do you know the manufactures' product(s) name(s)? Can you provide a link? Thanks,
Reply by ●July 7, 20062006-07-07
russell kym horsell wrote:> In comp.arch anon <cpu16x1832@wmconnect.com> wrote: > > For 1 instruction / nanosecond ( plus a nanosecond for on-chip ram > > access,) > [...] > > > I'm not sure whether you know this, but even several 5 year old GP chips with > clocks of 1 GHz (i.e. 1 ns cycle time for the pipelines) can > perform several (e.g. upto 10) operations in the 1 clock cycle -- even 1 to 4 > double precision fp ops.Do you know the manufactures' product(s) name(s)? Can you provide a link? Thanks,
Reply by ●July 7, 20062006-07-07
russell kym horsell wrote:> In comp.arch anon <cpu16x1832@wmconnect.com> wrote: > > For 1 instruction / nanosecond ( plus a nanosecond for on-chip ram > > access,) > > > > So far my possible architecture list includes, > > > > 1) A general purpose architecture, > > http://groups.google.com/group/comp.lang.java.machine/browse_frm/thre... > > > > 2) An embedded appliance architecture, > > http://www.elecdesign.com/Articles/Print.cfm?AD=1&ArticleID=12692 > > > > Do you have more links to other websites? > > > > Thanks, > > > > anon > > > I'm not sure whether you know this, but even several 5 year old GP chips with > clocks of 1 GHz (i.e. 1 ns cycle time for the pipelines) can > perform several (e.g. upto 10) operations in the 1 clock cycle -- even 1 to 4 > double precision fp ops.Do you know the manufactures' product(s) name(s) or website(s) that, for example, proclaim somewhere that fetching a variable's value from ram and adding that value with an accumulator requires only 5 nanoseconds before the result is ready to write to the data bus? Do you have links to websites?
Reply by ●July 9, 20062006-07-09
anon wrote:> russell kym horsell wrote: > >>In comp.arch anon <cpu16x1832@wmconnect.com> wrote: >> >>>For 1 instruction / nanosecond ( plus a nanosecond for on-chip ram >>>access,) >>> >>>So far my possible architecture list includes, >>> >>>1) A general purpose architecture, >>>http://groups.google.com/group/comp.lang.java.machine/browse_frm/thre... >>> >>>2) An embedded appliance architecture, >>>http://www.elecdesign.com/Articles/Print.cfm?AD=1&ArticleID=12692 >>> >>>Do you have more links to other websites? >>> >>>Thanks, >>> >>>anon >> >> >>I'm not sure whether you know this, but even several 5 year old GP chips with >>clocks of 1 GHz (i.e. 1 ns cycle time for the pipelines) can >>perform several (e.g. upto 10) operations in the 1 clock cycle -- even 1 to 4 >>double precision fp ops. > > > Do you know the manufactures' product(s) name(s) or website(s) that, > for example, proclaim somewhere that fetching a variable's value from > ram and adding that value with an accumulator requires only 5 > nanoseconds before the result is ready to write to the data bus? > > Do you have links to websites? >www.ibm.com www.intel.com www.amd.com And there is always the mips processor by i think, broadcom. And "accumulator" is so 1965, isn't it? del -- Del Cecchi "This post is my own and doesn�t necessarily represent IBM�s positions, strategies or opinions.�
Reply by ●July 9, 20062006-07-09
Plenty of these type of things: In comp.arch anon <cpu16x1832@wmconnect.com> wrote:> russell kym horsell wrote: > > In comp.arch anon <cpu16x1832@wmconnect.com> wrote: > > I'm not sure whether you know this, but even several 5 year old GP chips with[...]> > clocks of 1 GHz (i.e. 1 ns cycle time for the pipelines) can > > perform several (e.g. upto 10) operations in the 1 clock cycle -- even 1 to 4 > > double precision fp ops. > Do you know the manufactures' product(s) name(s) or website(s) that, >[...]I guess pipeline technology is a new term form many. As I said, almost all modern desktops -- e.g. those sporting intel x86, amd x86 & amd64 -- have multiple pipelines that allow multiple operations to be performed simultaneously. With a modest amount of software trickery (instruction scheduling) it's possible to execute an average (NB) of 1 instruction per clock cycle or even more for nice & regular algorithms like matrix multiply (a kinda workhorse for most statistical/mathematical software). I know many would probably like a complete bibliography, but I get 10 c for each time any of youzes hit google with a kw search.
Reply by ●July 9, 20062006-07-09
russell kym horsell wrote:> Plenty of these type of things: > > > In comp.arch anon <cpu16x1832@wmconnect.com> wrote: > > russell kym horsell wrote: > > > In comp.arch anon <cpu16x1832@wmconnect.com> wrote: > > > I'm not sure whether you know this, but even several 5 year old GP chips with > [...] > > > clocks of 1 GHz (i.e. 1 ns cycle time for the pipelines) can > > > perform several (e.g. upto 10) operations in the 1 clock cycle -- even 1 to 4 > > > double precision fp ops. > > Do you know the manufactures' product(s) name(s) or website(s) that, > >[...] > > > I guess pipeline technology is a new term form many. As I said, almost all > modern desktops -- e.g. those sporting intel x86, amd x86 & amd64 -- have > multiple pipelines that allow multiple operations to be performed > simultaneously. With a modest amount of software trickery (instruction > scheduling) it's possible to execute an average (NB) of 1 instruction per > clock cycle or even more for nice & regular algorithms like matrix multiply > (a kinda workhorse for most statistical/mathematical software). > > I know many would probably like a complete bibliography, but I get 10 c for > each time any of youzes hit google with a kw search.Pipelining DOESN'T reduce execution time of individual instructions, it statistically increases it! Pipelining DOES increase THE RATE at which INSTRUCTION STREAMS complete execution, however, NO SINGLE INSTRUCTION RUNS FASTER! My example urls, at the top of my request for information post, reference parallel processors and may execute DOZENS of INSTRUCTION STREAMS SIMULTANEOUSLY!!! DOZENS of Ghz ( in parrallel) is SIGNIFICANTLY GREATER than 1 GHz stuck inside an ancient pipeline architecture. Maybe read the URL(s) I gave you and THEN provide an actual reference, for example, "What is Piplining?" http://www.scism.sbu.ac.uk/ccsv/josephmb/CS-L2-MT/week6.html#3.1 Regards,
Reply by ●July 9, 20062006-07-09
russell kym horsell wrote:> Plenty of these type of things: > > > In comp.arch anon <cpu16x1...@wmconnect.com> wrote: > > russell kym horsell wrote: > > > In comp.arch anon <cpu16x1...@wmconnect.com> wrote: > > > I'm not sure whether you know this, but even several 5 year old GP chips with > [...] > > > clocks of 1 GHz (i.e. 1 ns cycle time for the pipelines) can > > > perform several (e.g. upto 10) operations in the 1 clock cycle -- even 1 to 4 > > > double precision fp ops. > > Do you know the manufactures' product(s) name(s) or website(s) that, > >[...] > > > I guess pipeline technology is a new term form many. As I said, almost all > modern desktops -- e.g. those sporting intel x86, amd x86 & amd64 -- have > multiple pipelines that allow multiple operations to be performed > simultaneously. With a modest amount of software trickery (instruction > scheduling) it's possible to execute an average (NB) of 1 instruction per > clock cycle or even more for nice & regular algorithms like matrix multiply > (a kinda workhorse for most statistical/mathematical software). > > I know many would probably like a complete bibliography, but I get 10 c for > each time any of youzes hit google with a kw search.Pipelining DOESN'T reduce execution time of individual instructions, it statistically increases it! Pipelining DOES increase THE RATE at which INSTRUCTION STREAMS complete execution, however, NO SINGLE INSTRUCTION RUNS FASTER! My example urls, at the top of my request for information post, reference parallel processors and may execute DOZENS of INSTRUCTION STREAMS SIMULTANEOUSLY!!! DOZENS of Ghz ( in parrallel) is SIGNIFICANTLY GREATER than 1 GHz stuck inside an ancient pipeline architecture. Maybe, for politeness, read the URL(s) I gave you and THEN provide an actual reference, for example, A 1 instruction / nanosecond plus a nanosecond for on-chip ram access counter example reference URL, "What is Piplining?" http://www.scism.sbu.ac.uk/ccsv/josephmb/CS-L2-MT/week6.html#3.1 Regards,
