Hello, Um, I know this is a DSP forum but I can't find any similar discussion groups for analog devices, and there seems to be a wide range of useful subjects discussed on these boards so I am hoping someone can give me some pointers. I am having a problem with an ADC evaluation board I purchased recently (AD7266). The board comes with an optional Eval-Board-Controller, which can be used (via a 96-way connector) to provide the necessary SCLK, Chip Select, power etc. signals and to read the ADC digital data. The same signals can be provided externally, and the appropriate links on the board must be set to the correct position to indicate what the source of these signals is (Eval-Board-Controller or externally supplied by the user). Now, I couldn't afford to purchase the controller, but I was hoping that I could still configure the board to use the 96-way connector to read the SCLK and CS signals from FPGA header pins, and likewise write the ADC data to the FPGA using the pins that on the 96-way connector pin-out are designated as the Serial-Data-In pins for the Eval-Board-Controller. I need to do this since the header on the FPGA board I am using is the only I/O on the board. My problem is as follows: The technical note implies that the Eval-Board-Controller supplies four clock sources labelled SCLK0 (on two pins) and SCLK1 (on two pins). In the schematic diagram these pins are all tied together at a common junction before being fed to the SCLK pin of the ADC. I don't know if the '1' and '0' refers to the polarity of the clock signal. I wondered if I would need to have four similarly configured sources, but I decided to just use one clock source to drive the SCLK pin. When I do this, I see the clock signal (centred about ground) on what should be the data output pins, and on the analog input pins. I am hoping this doesn't mean I have damaged the board, but does anyone have any suggestions about how I can safely use the 96-way connector as an interface with the FPGA, and avoid the problems described above? Thanks. mees
ADC evaluation board problem
Started by ●July 27, 2006
Reply by ●July 27, 20062006-07-27
mees wrote: ...> I am hoping this doesn't mean I have damaged the board, but does anyone > have any suggestions about how I can safely use the 96-way connector as an > interface with the FPGA, and avoid the problems described above?Have you tried talking to AD technical people on the phone? I've found them very helpful in the past. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������