Scalability of DSP Processors !

Hi everybody,
             can anyone tell me what does the scalability of DSP
processors mean. is it related to the MIPS of processor with per
instruction or related to functionality of the processor such as how
much operations a procressor can perform.
             If any one have other issues relates to this feature of
DSP Processors plz share with me. 

thanks

"prithvi" <prithvi.in@gmail.com> writes:

> Hi everybody,
>              can anyone tell me what does the scalability of DSP
> processors mean. is it related to the MIPS of processor with per
> instruction or related to functionality of the processor such as how
> much operations a procressor can perform.
>              If any one have other issues relates to this feature of
> DSP Processors plz share with me. 
> 

My understanding of this term (which may or may not relate to how it
is used in the context you have seen it...) is that it refers to the
ability of a particular DSP processor to be hooked up in multi-DSP
arrays easily.

For example:

* the Analog Devices Sharc family has link ports which enable
  inter-DSP comms to be done with low-overhead, this is good for
  scalability.

* The old TI C40s and Inmos transputers had their own style of link
  ports - also good.

* The current TI C6x family does not have any good ways for linking
  DSPs, so I don't feel they scale as well.

Does that help any?

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt