Hello Group, I'm trying to use a general purpose timer to generate periodic interrupts on the Blackfin BF561. I have the EZ-KIT, and I can't find any good examples to accomplish this. I've read the manual and set the registers as follows in the code snippet. I do clear the status bit in the timer0 ISR. I have the timer in PWM_OUT mode. I'm wondering what I'm doing wrong cause it just won't trigger an interrupt. I *have* figured out how to get the core timer to interrupt properly. <--- code snippet ---> //p15-13 in processor hardware reference manual // 0000 0000 0001 1001 // IRQ_ENA = 1 Enable the interrupt request. // PERIOD_CNT = 1 // TMODE = 01 <- PWM_OUT mode --cja *pTIMER0_CONFIG = 0x0019; ssync(); //SCLK = 2^27 or 133MHz //Clock Period = (TIMERx_PERIOD-1)/SCLK //Frequency = 1/Clock Period //TIMERx_PERIOD=SCLK/Freq - 1 <-- use this eqn --cja *pTIMER0_PERIOD = 0x0028F5C1; //This should be half of the period for 50% duty *pTIMER0_WIDTH = 0x00147AE0; //Just enable timer 0 for now. //Here is the 561 code *pTMRS8_ENABLE |= 0x0001; //enables the core interrupt nask register *pIMASK |= 0x0400; // assign interrupt channel 35 (Timer0) to IVG10 (p4-35) *pSICA_IAR4 = Peripheral_IVG(35,10); // Timer0 ISR -> IVG 10 --cja register_handler(ik_ivg10, Timer0_ISR); // clear pending IVG10 interrupts *pILAT |= EVT_IVG10; ssync(); // enable Timer0 interrupt (p4-35 hardware) *pSICA_IMASK1 |= SIC_MASK(3); ssync(); <--- code snippet ---> Thanks, Chris Arges Sumanth Peddamatham
Blackfin BF561/BF533 Timer problem/question.
Started by ●September 11, 2006