Forums

Systolic Viterbi Decoder ?

Started by BERT October 15, 2006
Hi,

Sorry for the cross-post, but I think this is a relevant topic in both
newsgroups.

Has anyone come across this paper ?

T.K. Troung, Ming-Tang Shih, I.S. Reed, E.H. Satorius, "A VLSI design
for a trace-back viterbi decoder", IEEE Tranactions on Communications,
Vol. 40, No. 3, March 1992.

They describe a register-based systolic approach to implement the
traceback that they claim requires "a minimal amount of storage and a
short decoding time", when compared to the register exchange and
traceback memory methods. I can see that this method would indeed
provide a short decoding time, but I don't agree with the storage
claim. For example, a rate 1/2, K = 9 code would require (256*2*45) +
8*45 = 23400 registers, just for the traceback portion (traceback
length = 45). Using the one-pointer traceback RAM method (which uses
the highest amount of RAM), we would need 45*256*4 = 46080 bits which
would I guess, would still be more area efficient to implement.

Is the traceback (RAM) method using the k-pointer (or R-pointer ??)
algorithms still the best way to go to implement traceback in viterbi
decoders (in terms of a decent tradeoff between area-efficiency and
decoding delay) ?

Thanks,
Vijay.