time to frequency measurement

alexs wrote:

> I need to measure the time it takes signal to turn on and be at steady
> state frequency (1 to 10MHz)to within 200hz resolution within 2us.  The
> kicker is that I can only sample at 65MSPS.  Is this possible?  I can
> get 200hz resolution by sampling for 5ms, but I am only interested in
> the sample from 0 to 2us, so when I window that section, I loose my
> resolution.  If this problem interests you, I can provide more
> information on request.

I would try another approach:
At first let's assume that the signal (at least sometimes) does settle
within 2us and into the band of 200Hz. Otherwise the task would be silly.

Then, the type of signal seems to be a sine wave or a square or alike,
which has a single steady frequency, once settled.

The process of settling will probably be controlled by a closed loop
mechanism (PLL), which may cause switching effects, but in the end mainly 
behave like a low pass filter or integrator.

This assumed, I'd propose to analyze this behavior.
As long as the transient part of the settling process dominates, you'll
hardly be able to esimate the settling time. There can be too much
influencing aspects (be it in hardware or in the synthesizer's algorithms).
But as soon, as the integrator dominates, you can probably estimate the
declining behavior and from that calculate the settling time quite well.

So you have to find out these two behavioral components of the signal
source: the transient part (only to be able to discriminate it from the
other) and the integral part. Then find the takeover between both of them.

After that analysis you should be able to decide if the task is solvable.
As an example, if the takeover point would be reached after a settling to
10% of the frequency, your task would become easier: you have to find out,
when the frequency reaches this new limit (which should be possible in much
less time), and then just estimate if the goal is reached by extrapolating
the integral equation.

Another issue (later on that way) is how you should measure the instantanous
frequency, if the target frequency can be anywhere between 1... 10MHz.
You'll probably need a sort of df/dt - looks like a frequency demodulator.

Do you have to solve this issue completely in software / after sampling?

Using a hardware approach based on an additional PLL might do a better job.

I wish you good luck for this really challenging task.
Bernhard

alexs wrote:
> I need to measure the time it takes signal to turn on and be at steady
> state frequency (1 to 10MHz)to within 200hz resolution within 2us.  The
> kicker is that I can only sample at 65MSPS.  Is this possible?  I can
> get 200hz resolution by sampling for 5ms, but I am only interested in
> the sample from 0 to 2us, so when I window that section, I loose my
> resolution.  If this problem interests you, I can provide more
> information on request.

Another approach is a time period measurement. To achieve the 200 Hz
resolution @ 10 MHz you will need to measure the period to within 20
ps. This is possible with time-to-digital converters:

http://www.acam.de/index.php?id=18&L=0

I don't think that you will be able to do it with your adc, which will
also have to have sampling jitter in the 20 ps range. Of course, as
mentioned before, the SNR of your signal will probably be the ultimate
limiting factor. There is no point in digitizing noise to a very high
degree of accuracy (unless you want a random number generator!).

Tom

OK, I didnt realize that I would attract alot of people on this one,
but more information is desired, so here it is.  It is desired that the
VCO locking for a wireless part I am testing on ATE settle to within
200hz of the desired and known steady state frequency within 2us (a
spec some customer wants) after a change in the state of the part.  For
example, shutdown to RX mode, or TX mode to RX mode, etc.  The part is
a transciever and the question was concerning the RX baseband output
signal although the same concept can be applied to the TX.  By
adjusting the input RF frequency and the internal PLL of the part, I
can get the output RX BB frequency to be anything I want within the
bandwidth of the internal filter of the part.  Since I need to test for
settling within 2us, I need the output frequency to be at least 1MHz,
but something like 10 would be more desireable because i would have
more cycles to deal with within that 2us time frame.  What would happen
is that when the parts gets programmed to RX mode, the signal at the
output will begin to turn on, ramp up, and stabalize to the desired
frequency (CW) and of course the desired signal level within 2us.  The
signal can be directly sampled by a digitizer sampling at 65MSPS with
14 bits resolution.  The standard relationship between frequency
resolution and time suggests that 5ms of data is required to get 200hz
of resolution, but this is over the entire sample.  I am really only
interested in the first 2us, as i already know via experimentation and
by programming the part what the frequency and signal level will be.  I
have thought about taking the first 2us of data, adding a ton of
zeroes, then taking the fft (effectivley reducing the resolution in the
frequency domain by increasing the number of samples in the time
domain).  Or do the FFT on the 2us window (I have to ensure here that
the sampling is coherent so I dont get frequency bleeding), add zeroes
in the frequency domain, then do an IFFT, and correlate that to a known
ideal sine wave.   But I have not the knowledge or experience to know
if this is a correct approach.

The other option is in hardware, not software, but that requires a
change to my board.  simply apply the RX BB into low frequency mixer
with the LO the same frequency as the RF, so I get DC out (filter the
2f garbage).  The point at which the output hits 0.5V is the settling
time.  There would be some voltage to frequency relationship to get the
200hz resolution resolved.  Or use a PLL as a FM demodulator, again,
change to my board.  I already have the digitized signal, the question
is, can it be done in software.

I hope this info helps.

alexs wrote:

> The other option is in hardware, not software, but that requires a
> change to my board.  simply apply the RX BB into low frequency mixer
> with the LO the same frequency as the RF, so I get DC out (filter the
> 2f garbage).  The point at which the output hits 0.5V is the settling
> time.  There would be some voltage to frequency relationship to get the
> 200hz resolution resolved.  Or use a PLL as a FM demodulator, again,
> change to my board.  I already have the digitized signal, the question
> is, can it be done in software.
> 

If this is an option, I would definitely vote for it:
Costs and time frame are very predictable, while software might impose lots
of difficulties, which are still unclear.

Do you have to solve the whole software issue during these 2us, or how much
(processing) time is available for the whole calculation?

Bernhard

"alexs" <alexs@pacifier.com> wrote in message 
news:1162527852.793075.109000@h54g2000cwb.googlegroups.com...
> OK, I didnt realize that I would attract alot of people on this one,
> but more information is desired, so here it is.  It is desired that the
> VCO locking for a wireless part I am testing on ATE settle to within
> 200hz of the desired and known steady state frequency within 2us (a
> spec some customer wants) after a change in the state of the part.  For
> example, shutdown to RX mode, or TX mode to RX mode, etc.  The part is
> a transciever and the question was concerning the RX baseband output
> signal although the same concept can be applied to the TX.  By
> adjusting the input RF frequency and the internal PLL of the part, I
> can get the output RX BB frequency to be anything I want within the
> bandwidth of the internal filter of the part.  Since I need to test for
> settling within 2us, I need the output frequency to be at least 1MHz,
> but something like 10 would be more desireable because i would have
> more cycles to deal with within that 2us time frame.  What would happen
> is that when the parts gets programmed to RX mode, the signal at the
> output will begin to turn on, ramp up, and stabalize to the desired
> frequency (CW) and of course the desired signal level within 2us.  The
> signal can be directly sampled by a digitizer sampling at 65MSPS with
> 14 bits resolution.  The standard relationship between frequency
> resolution and time suggests that 5ms of data is required to get 200hz
> of resolution, but this is over the entire sample.  I am really only
> interested in the first 2us, as i already know via experimentation and
> by programming the part what the frequency and signal level will be.  I
> have thought about taking the first 2us of data, adding a ton of
> zeroes, then taking the fft (effectivley reducing the resolution in the
> frequency domain by increasing the number of samples in the time
> domain).  Or do the FFT on the 2us window (I have to ensure here that
> the sampling is coherent so I dont get frequency bleeding), add zeroes
> in the frequency domain, then do an IFFT, and correlate that to a known
> ideal sine wave.   But I have not the knowledge or experience to know
> if this is a correct approach.
>
> The other option is in hardware, not software, but that requires a
> change to my board.  simply apply the RX BB into low frequency mixer
> with the LO the same frequency as the RF, so I get DC out (filter the
> 2f garbage).  The point at which the output hits 0.5V is the settling
> time.  There would be some voltage to frequency relationship to get the
> 200hz resolution resolved.  Or use a PLL as a FM demodulator, again,
> change to my board.  I already have the digitized signal, the question
> is, can it be done in software.
>
> I hope this info helps.
>
Would something like the Agilent 53132 counter be of use
(12 digits/sec)?

Manual here:
http://cp.literature.agilent.com/litweb/pdf/53131-90055.pdf

Regards
    Ian 

Although I am only interested in the time at and below 2us, I can take
as long as I like in post processing (not really, we have to make money
by keeping test time down).  But a few hundred ms would be perfectly
acceptable.

And like I said, this is ATE (Automatic Test Equipment), I am relegated
to the tester that is provided me, which is an RF tester manufactured
by Credence.  It doesnt have the Agilent counter.

So the question is, is there a trick in DSP land in which this can be
done with my sampling rate and 14 bit resolution.

Alex

alexs wrote:
> Although I am only interested in the time at and below 2us, I can take
> as long as I like in post processing (not really, we have to make money
> by keeping test time down).  But a few hundred ms would be perfectly
> acceptable.
>
> And like I said, this is ATE (Automatic Test Equipment), I am relegated
> to the tester that is provided me, which is an RF tester manufactured
> by Credence.  It doesnt have the Agilent counter.
>
> So the question is, is there a trick in DSP land in which this can be
> done with my sampling rate and 14 bit resolution.
>
> Alex

Well, NO. There is NO MAGIC way that you can create information that
DOES NOT EXIST. You have what seems to be an arbitrary specification
that you are trying to meet with minimal effort. Given that the magic
bullet you are looking for is ellusive by simple mathematics, I
recommend de-scoping to resolve the issue (change the specifications to
something that is realistic).

Tom

alexs wrote:

> 
> So the question is, is there a trick in DSP land in which this can be
> done with my sampling rate and 14 bit resolution.
> 


With a signal of 1MHz, you'd have 4 subsequent zero crossings within 2us.
That's poor. A frequency domain analysis would require more. 
So let's try in the time domain...
If the jitter (timing uncertainty) analysis of your ADC allows,
you might watch the zero crossings of the signal.
The "acceleration" between the subsequent distances of zero crossings should
reveal the trend of the settling curve.
Provided that you have a typical settling curve (derived from the circuit
parameters), even this small number of measurements might be enough to
qualify the result.

As a check if this works:
Plot several typical settling curves around the critical value.
Then insert the measured zero crossings into these plots and check, if the
discrimination rate suffices.

If not, try with the derivatives of the curves and/or the measurements.
Since you're interested in the  "acceleration" of the zero-crossing distance
curve, you might be successful when evaluating the first and/or second
order derivatives.

But it depends on the jitter of the ADC as on the purity of the signal.
If either is too bad, the errors might hide the effect.
In one application where I used such a zero-crossings method, I had to
"adjust" the measurements by evaluating more than a single sample to
determine the position of the zero-crossing. Simple averaging helped to
overcome the poor measurement arrangement.

Bernhard

Since the purpose of this is to monitor the frequency at at startup 
produced by the VCO for compliance to a time until stable output, 
perhaps a different approach may work.  What if you monitored the VCO 
control voltage, which will have a pretty much 1:1 relationship to the 
VCO frequency less some temperature variation and a time lag that has a 
maximum specified in the VCO data sheet.  I think you can use that 
control voltage, plus the VCO data sheet to analytically arrive at a 
compliance measurement that is at least as accurate as trying to measure 
the frequency in a 2us interval (part of which the frequency is 
slewing), and that avoids the issues with trying to determine a signal 
frequency within a tight tolerance from an abbreviated sample.

You didn't provide enough information about your problem.
What is your signal ? What is your SNR ?

You just might have to forget about FFT and do it all in time domain.

As far as time-domain frequency estimation is concerned,
the place to go for a definitive answer is www.uspto.gov/patft
United Stated Patent 7,124,075 has everything you need to start...
(Non-commercial use is fine)

And BTW, this is a textbook material for future DSP students :-)


alexs wrote:
> I need to measure the time it takes signal to turn on and be at steady
> state frequency (1 to 10MHz)to within 200hz resolution within 2us.  The
> kicker is that I can only sample at 65MSPS.  Is this possible?  I can
> get 200hz resolution by sampling for 5ms, but I am only interested in
> the sample from 0 to 2us, so when I window that section, I loose my
> resolution.  If this problem interests you, I can provide more
> information on request.