# DSP sample rate question

Started by June 9, 2004
```Hello,

I have a quick question. Say I am working on a DSP low pass filter that
will be utilizing a 10Hz cutoff frequency. This is a two pole butterworth
based recursive (IIR) filter. I -think- our highest frequency component
will most likely be (rate of change in digital input to the IIR) around
8kHz. My manager who is primarily experienced in analog filter thinks that
we'll only need to watch this change at 20 Hz sampling rate or so. I think
we have to allow the full 8kHz change rate (sample) pass through. At his
speed the DSP software would have no problem processing it. At my gut
feeling speed of 8kHz I think we'll be pushing if not exceeding the
computational bounds of the DSP (onboard FPGA, @ 1 or 2 Megahertz clock).
I haven't really sat down to work these number of computations out, as
we haven't implemented even the multiply/accumulate functions yet, but I
do think it's a "big deal" and will be one of our hurdles. So I guess is
it 20 or is it 8000 ?

Thanks,
Jon
```
```Jon Dohnson wrote:

> Hello,
>
> I have a quick question. Say I am working on a DSP low pass filter that
> will be utilizing a 10Hz cutoff frequency. This is a two pole butterworth
> based recursive (IIR) filter. I -think- our highest frequency component
> will most likely be (rate of change in digital input to the IIR) around
> 8kHz. My manager who is primarily experienced in analog filter thinks that
> we'll only need to watch this change at 20 Hz sampling rate or so. I think
> we have to allow the full 8kHz change rate (sample) pass through. At his
> speed the DSP software would have no problem processing it. At my gut
> feeling speed of 8kHz I think we'll be pushing if not exceeding the
> computational bounds of the DSP (onboard FPGA, @ 1 or 2 Megahertz clock).
> I haven't really sat down to work these number of computations out, as
> we haven't implemented even the multiply/accumulate functions yet, but I
> do think it's a "big deal" and will be one of our hurdles. So I guess is
> it 20 or is it 8000 ?
>
> Thanks,
> Jon

In order to reduce a digital signal to a 20-Hz sample rate without
aliasing, it must first be filtered to 10 Hz or less, thereby
eliminating all component frequencies higher than half the sample rate
as required by the Shannon sampling theorem. In other words, once you
filter your signal with your proposed filter, then you can reduce its
sample rate. Perhaps that's what your manager means.

Make sure that the original signal is bandlimited to not more than half
the original sample rate. If it isn't, it's already contaminated.

Jerry
--
Engineering is the art of making what you want from things you can get.
&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;

```
```On Wed, 09 Jun 2004 11:34:37 -0400, Jon Dohnson wrote:

> Hello,
>
> I have a quick question. Say I am working on a DSP low pass filter that
> will be utilizing a 10Hz cutoff frequency. This is a two pole butterworth
> based recursive (IIR) filter. I -think- our highest frequency component
> will most likely be (rate of change in digital input to the IIR) around
> 8kHz. My manager who is primarily experienced in analog filter thinks that
> we'll only need to watch this change at 20 Hz sampling rate or so. I think
> we have to allow the full 8kHz change rate (sample) pass through. At his
> speed the DSP software would have no problem processing it. At my gut
> feeling speed of 8kHz I think we'll be pushing if not exceeding the
> computational bounds of the DSP (onboard FPGA, @ 1 or 2 Megahertz clock).
> I haven't really sat down to work these number of computations out, as
> we haven't implemented even the multiply/accumulate functions yet, but I
> do think it's a "big deal" and will be one of our hurdles. So I guess is
> it 20 or is it 8000 ?
>
> Thanks,
> Jon

an error function with 10bits of accuracy which will be changing the most
8k times per second. So I don't think I'll be needing any low pass
filtering on the input to avoid aliasing. I should have added this in
my original post. Not enough coffee I guess :) .

```
```Jon,

That's 'junior' DSP for an FPGA, especially as you only need a 2 order
on multi-rate filtering, decimation in particular. You can use cascaded
low-pass filters to reduce the sampling rate and avoid aliasing. The book I
use is 'Multirate Digital Signal Processing' by Crochiere and Rabiner.
Have fun, Syms.
"Jon Dohnson" <jon_dohnson@nothanks.usenet.only.com> wrote in message
news:pan.2004.06.09.15.34.36.590000@nothanks.usenet.only.com...
> Hello,
>
> I have a quick question. Say I am working on a DSP low pass filter that
> will be utilizing a 10Hz cutoff frequency. This is a two pole butterworth
> based recursive (IIR) filter. I -think- our highest frequency component
> will most likely be (rate of change in digital input to the IIR) around
> 8kHz. My manager who is primarily experienced in analog filter thinks that
> we'll only need to watch this change at 20 Hz sampling rate or so. I think
> we have to allow the full 8kHz change rate (sample) pass through. At his
> speed the DSP software would have no problem processing it. At my gut
> feeling speed of 8kHz I think we'll be pushing if not exceeding the
> computational bounds of the DSP (onboard FPGA, @ 1 or 2 Megahertz clock).
> I haven't really sat down to work these number of computations out, as
> we haven't implemented even the multiply/accumulate functions yet, but I
> do think it's a "big deal" and will be one of our hurdles. So I guess is
> it 20 or is it 8000 ?
>
> Thanks,
> Jon

```
```"Jon Dohnson" <jon_dohnson@nothanks.usenet.only.com> wrote in message
news:pan.2004.06.09.17.28.55.92000@nothanks.usenet.only.com...
> On Wed, 09 Jun 2004 11:34:37 -0400, Jon Dohnson wrote:
>
> > Hello,
> >
> > I have a quick question. Say I am working on a DSP low pass filter that
> > will be utilizing a 10Hz cutoff frequency. This is a two pole butterworth
> > based recursive (IIR) filter. I -think- our highest frequency component
> > will most likely be (rate of change in digital input to the IIR) around
> > 8kHz. My manager who is primarily experienced in analog filter thinks that
> > we'll only need to watch this change at 20 Hz sampling rate or so. I think
> > we have to allow the full 8kHz change rate (sample) pass through. At his
> > speed the DSP software would have no problem processing it. At my gut
> > feeling speed of 8kHz I think we'll be pushing if not exceeding the
> > computational bounds of the DSP (onboard FPGA, @ 1 or 2 Megahertz clock).
> > I haven't really sat down to work these number of computations out, as
> > we haven't implemented even the multiply/accumulate functions yet, but I
> > do think it's a "big deal" and will be one of our hurdles. So I guess is
> > it 20 or is it 8000 ?
>
> I should also add to my own post. This is not an analog input signal. It's
> an error function with 10bits of accuracy which will be changing the most
> 8k times per second. So I don't think I'll be needing any low pass
> filtering on the input to avoid aliasing. I should have added this in
> my original post. Not enough coffee I guess :) .

If you were to simply look at only 1 out of every 400 data points (which is what
I think your manager is suggesting) you would have aliening.  If the original
input signal had a frequency component at for example 21Hz, and you decimated to
20Hz, this would show up as a 1Hz signal.  Now, your 10Hz cut-off LP filter
would not attenuate this component, whereas if you operated the filter at 8kHz,
it would have.  That is practically why you can't simply throw away the data to
reduce the sample rate.  (The exception would be if the data was already
band-limited to the 10Hz, but that doesn't sound like the case in your
situation.)

```
```Symon wrote:

> Jon,
>
> That's 'junior' DSP for an FPGA, especially as you only need a 2 order
> Butterworth response. If you're still worried about processing rate, read up
> on multi-rate filtering, decimation in particular. You can use cascaded
> low-pass filters to reduce the sampling rate and avoid aliasing. The book I
> use is 'Multirate Digital Signal Processing' by Crochiere and Rabiner.
> Have fun, Syms.
> "Jon Dohnson" <jon_dohnson@nothanks.usenet.only.com> wrote in message
> news:pan.2004.06.09.15.34.36.590000@nothanks.usenet.only.com...
>
>>Hello,
>>
>>I have a quick question. Say I am working on a DSP low pass filter that
>>will be utilizing a 10Hz cutoff frequency. This is a two pole butterworth
>>based recursive (IIR) filter. I -think- our highest frequency component
>>will most likely be (rate of change in digital input to the IIR) around
>>8kHz. My manager who is primarily experienced in analog filter thinks that
>>we'll only need to watch this change at 20 Hz sampling rate or so. I think
>>we have to allow the full 8kHz change rate (sample) pass through. At his
>>speed the DSP software would have no problem processing it. At my gut
>>feeling speed of 8kHz I think we'll be pushing if not exceeding the
>>computational bounds of the DSP (onboard FPGA, @ 1 or 2 Megahertz clock).
>>I haven't really sat down to work these number of computations out, as
>>we haven't implemented even the multiply/accumulate functions yet, but I
>>do think it's a "big deal" and will be one of our hurdles. So I guess is
>>it 20 or is it 8000 ?
>>
>>Thanks,
>>Jon
>
>
>

Certainly you should be able to filter an 8kHz signal with an FPGA
clocked at 1MHz.  In fact, if it's big enough you should be able to
implement your filter an an FPGA clocked at 8kHz -- you'll just need
lots and lots of parallelism.

And look at your filtering requirements.  Assuming that you don't have
much FPGA space to spare you may be able to get by simply by averaging
and decimating (i.e. take the sum of 800 samples, and output that at
10Hz).  It's a pretty cheesy filter, but it falls off pretty fast and it
has a zero every 10Hz.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
```
```Jon Dohnson wrote:

> On Wed, 09 Jun 2004 11:34:37 -0400, Jon Dohnson wrote:
>
>
>>Hello,
>>
>>I have a quick question. Say I am working on a DSP low pass filter that
>>will be utilizing a 10Hz cutoff frequency. This is a two pole butterworth
>>based recursive (IIR) filter. I -think- our highest frequency component
>>will most likely be (rate of change in digital input to the IIR) around
>>8kHz. My manager who is primarily experienced in analog filter thinks that
>>we'll only need to watch this change at 20 Hz sampling rate or so. I think
>>we have to allow the full 8kHz change rate (sample) pass through. At his
>>speed the DSP software would have no problem processing it. At my gut
>>feeling speed of 8kHz I think we'll be pushing if not exceeding the
>>computational bounds of the DSP (onboard FPGA, @ 1 or 2 Megahertz clock).
>>I haven't really sat down to work these number of computations out, as
>>we haven't implemented even the multiply/accumulate functions yet, but I
>>do think it's a "big deal" and will be one of our hurdles. So I guess is
>>it 20 or is it 8000 ?
>>
>>Thanks,
>>Jon
>
>
> I should also add to my own post. This is not an analog input signal. It's
> an error function with 10bits of accuracy which will be changing the most
> 8k times per second. So I don't think I'll be needing any low pass
> filtering on the input to avoid aliasing. I should have added this in
> my original post. Not enough coffee I guess :) .

I'm not at ease with such signals. I hope some of the others here can
shed some light. That this signal can change 8000 times a second could
be interpreted to mean that it can have a component at 8000 Hz, which
makes it undersampled by a factor of two, with all the attendant
difficulties that raises. On the other hand, 1, -1, 1, -1, ... at 8000
samples a second represents only 4000 Hz, which is fine. I've seen only
contrived cases where the assumption of 4000 Hz actually led to trouble.

Either way, it would be foolish to assume 20 Hz, which, to take you
literally, seems to be what your boss wants to do.

Jerry
--
Engineering is the art of making what you want from things you can get.
&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;

```