Forums

FMDemod, Phase noise and Polyphase

Started by Yip December 3, 2006
Hi All,

I am trying to debug a FM demodulation noise problem for a FPGA
prototype. The output in general looks ok, but the THD+N of a clean 60%
modulated signal is only in the mid-40's dB (noticable even by ear),
and that is mainly due to a high noise floor. The FM architecture is
using the differentiator approach dAtan(Q/I)/dt with  [1 -1] as the
differentiator. (Phase wrap-around at +/-pi and pre/deemphasis also has
been taken cared of).

One of the main concerns not too sure about is the phase noise in the
system since it is running on a FPGA.

In addition, there are some bin-based polyphase filters between the
input ADC and the FM Demod to make up the differences in their possible
sampling rates. I recall for a M/N integer fractional ratio, a
polyphase should be equivalent to a Upsampling-Downsampling filter with
the intermediate parts cancelled out mathematically.

However, can this bin-based architecture able to hold out for the case
of the non-integer fractional steps? The gut feeling is a bit insecure
since there are Approximations involved to the resampling phases during
the process. Will this type of polyphase architecture generate extra
phase noises to the data that get propagated to the output noise?

Also, are there any ways to help improve robustness of FM demodulation
against phase noise in general (ie. phase noise due to clock jitters
and uneven sampling rates on the FPGA and etc)?

Finally, are there other common possible causes for the poor
performance that I missed?

Any help is appreciated. Thanks in advance.


Yip wrote:

> Hi All, > > I am trying to debug a FM demodulation noise problem for a FPGA > prototype. The output in general looks ok, but the THD+N of a clean 60% > modulated signal is only in the mid-40's dB (noticable even by ear), > and that is mainly due to a high noise floor.
How does the output look like on the clean unmodulated carrier? The FM architecture is
> using the differentiator approach dAtan(Q/I)/dt with [1 -1] as the > differentiator.
[1 -1] as a differentiator is not good idea. The THD will be limited by the accuracy of the differentiator unless you employ a ridiculously high oversampling ratio. You should use a good FIR differentiator.
> One of the main concerns not too sure about is the phase noise in the > system since it is running on a FPGA.
It should not be a problem.
> > In addition, there are some bin-based polyphase filters between the > input ADC and the FM Demod to make up the differences in their possible > sampling rates.
Any kind of bandlimiting on the FM will result in the increase in THD. Make sure the bandwidth is wide enough. I recall for a M/N integer fractional ratio, a
> polyphase should be equivalent to a Upsampling-Downsampling filter with > the intermediate parts cancelled out mathematically. > However, can this bin-based architecture able to hold out for the case > of the non-integer fractional steps? The gut feeling is a bit insecure > since there are Approximations involved to the resampling phases during > the process. Will this type of polyphase architecture generate extra > phase noises to the data that get propagated to the output noise?
It sounds too complex. I can't get it. Tell me what are you trying to accomplish.
> Also, are there any ways to help improve robustness of FM demodulation > against phase noise in general (ie. phase noise due to clock jitters > and uneven sampling rates on the FPGA and etc)?
If the FM parameters are reasonable, then the impact of those noises should be a miser.
> > Finally, are there other common possible causes for the poor > performance that I missed?
The FM discriminator is pretty straightforward. The only reason for poor operation could be a bug somewhere. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Thanks for the fast reply.

Vladimir Vassilevsky wrote:
> Yip wrote: > > > Hi All, > > > > I am trying to debug a FM demodulation noise problem for a FPGA > > prototype. The output in general looks ok, but the THD+N of a clean 60% > > modulated signal is only in the mid-40's dB (noticable even by ear), > > and that is mainly due to a high noise floor. > > How does the output look like on the clean unmodulated carrier?
The output for the case of the clean unmodulated carrier contains the same noise in the spectrum analyzer as the other one.
> > > The FM architecture is > > using the differentiator approach dAtan(Q/I)/dt with [1 -1] as the > > differentiator. > > [1 -1] as a differentiator is not good idea. The THD will be limited by > the accuracy of the differentiator unless you employ a ridiculously high > oversampling ratio. You should use a good FIR differentiator.
The [1 -1] differentiator currently runs at ~1.5MHz sampling rate for a currently 15kHz deviation signal (60% of a 25kHz = 100% deviation). Is this considered a high or low oversampling ratio?
> > > > One of the main concerns not too sure about is the phase noise in the > > system since it is running on a FPGA. > > It should not be a problem. > > > > > In addition, there are some bin-based polyphase filters between the > > input ADC and the FM Demod to make up the differences in their possible > > sampling rates. > > Any kind of bandlimiting on the FM will result in the increase in THD. > Make sure the bandwidth is wide enough.
The bandlimiting occurs over a couple of Carson BW away (only in the range for filtering out adjacent channels if there is any).
> > I recall for a M/N integer fractional ratio, a > > polyphase should be equivalent to a Upsampling-Downsampling filter with > > the intermediate parts cancelled out mathematically. > > However, can this bin-based architecture able to hold out for the case > > of the non-integer fractional steps? The gut feeling is a bit insecure > > since there are Approximations involved to the resampling phases during > > the process. Will this type of polyphase architecture generate extra > > phase noises to the data that get propagated to the output noise? > > It sounds too complex. I can't get it. > Tell me what are you trying to accomplish.
The problem is the rate which the FMDemod is run is not a "nice" ratio of the rate of the ADC to the FPGA is run. Thus, there are non-integer ratio resampling processes implemented via polyphase resamplers. However due to there are only finite # of bins in the polyphase filter bank, the resampling phases has quantizations when indexed into the polyphase filter banks. I am not sure if that may cause problems down the road or not.
> > > Also, are there any ways to help improve robustness of FM demodulation > > against phase noise in general (ie. phase noise due to clock jitters > > and uneven sampling rates on the FPGA and etc)? > > If the FM parameters are reasonable, then the impact of those noises > should be a miser. > > > > > Finally, are there other common possible causes for the poor > > performance that I missed? > > The FM discriminator is pretty straightforward. The only reason for poor > operation could be a bug somewhere. > > > Vladimir Vassilevsky > > DSP and Mixed Signal Design Consultant > > http://www.abvolt.com
Thanks again.
Vladimir Vassilevsky wrote:
> > > Yip wrote: > >> Hi All, >> >> I am trying to debug a FM demodulation noise problem for a FPGA >> prototype. The output in general looks ok, but the THD+N of a clean 60% >> modulated signal is only in the mid-40's dB (noticable even by ear), >> and that is mainly due to a high noise floor. > > How does the output look like on the clean unmodulated carrier? > > > The FM architecture is >> using the differentiator approach dAtan(Q/I)/dt with [1 -1] as the >> differentiator.
I, Q, and dAtan(Q/I)/dt all need to refer to the same instant. In other words, the processing delays for each must be the same as for all the others.
> [1 -1] as a differentiator is not good idea. The THD will be limited by > the accuracy of the differentiator unless you employ a ridiculously high > oversampling ratio. You should use a good FIR differentiator.
[1 -1] *is* an FIR differentiator, just not a good one. It is particularly bad in have a half-sample delay, which is hard to match in I and Q. ...
>> Finally, are there other common possible causes for the poor >> performance that I missed? > > The FM discriminator is pretty straightforward. The only reason for poor > operation could be a bug somewhere.
Such as a failure to equalize all processing delays. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Yip wrote:
> Hi All, > > I am trying to debug a FM demodulation noise problem for a FPGA > prototype. The output in general looks ok, but the THD+N of a clean 60% > modulated signal is only in the mid-40's dB (noticable even by ear), > and that is mainly due to a high noise floor. The FM architecture is > using the differentiator approach dAtan(Q/I)/dt with [1 -1] as the > differentiator. (Phase wrap-around at +/-pi and pre/deemphasis also has > been taken cared of). > > One of the main concerns not too sure about is the phase noise in the > system since it is running on a FPGA. > > In addition, there are some bin-based polyphase filters between the > input ADC and the FM Demod to make up the differences in their possible > sampling rates. I recall for a M/N integer fractional ratio, a > polyphase should be equivalent to a Upsampling-Downsampling filter with > the intermediate parts cancelled out mathematically. > > However, can this bin-based architecture able to hold out for the case > of the non-integer fractional steps? The gut feeling is a bit insecure > since there are Approximations involved to the resampling phases during > the process. Will this type of polyphase architecture generate extra > phase noises to the data that get propagated to the output noise? >
Are the ADC, FPGA, and DAC clocks synchronous? Is your resampler jumping between the phases? John
"Yip" <yipkingsui@hotmail.com> writes:

> Hi All, > > I am trying to debug a FM demodulation noise problem for a FPGA > prototype. The output in general looks ok, but the THD+N of a clean 60% > modulated signal is only in the mid-40's dB (noticable even by ear), > and that is mainly due to a high noise floor. The FM architecture is > using the differentiator approach dAtan(Q/I)/dt with [1 -1] as the > differentiator. (Phase wrap-around at +/-pi and pre/deemphasis also has > been taken cared of). > > One of the main concerns not too sure about is the phase noise in the > system since it is running on a FPGA. > > In addition, there are some bin-based polyphase filters between the > input ADC and the FM Demod to make up the differences in their possible > sampling rates. I recall for a M/N integer fractional ratio, a > polyphase should be equivalent to a Upsampling-Downsampling filter with > the intermediate parts cancelled out mathematically. > > However, can this bin-based architecture able to hold out for the case > of the non-integer fractional steps? The gut feeling is a bit insecure > since there are Approximations involved to the resampling phases during > the process. Will this type of polyphase architecture generate extra > phase noises to the data that get propagated to the output noise? > > Also, are there any ways to help improve robustness of FM demodulation > against phase noise in general (ie. phase noise due to clock jitters > and uneven sampling rates on the FPGA and etc)? > > Finally, are there other common possible causes for the poor > performance that I missed? > > Any help is appreciated. Thanks in advance.
How about starting from the top down: Is it analog or digital? That is, have you checked the analog input(s) to the ADC with a spectrum analyzer? Are they clean? -- % Randy Yates % "Ticket to the moon, flight leaves here today %% Fuquay-Varina, NC % from Satellite 2" %%% 919-577-9882 % 'Ticket To The Moon' %%%% <yates@ieee.org> % *Time*, Electric Light Orchestra http://home.earthlink.net/~yatescr
Yip wrote:

> Hi All, > > I am trying to debug a FM demodulation noise problem for a FPGA > prototype. The output in general looks ok, but the THD+N of a clean 60% > modulated signal is only in the mid-40's dB (noticable even by ear), > and that is mainly due to a high noise floor. The FM architecture is > using the differentiator approach dAtan(Q/I)/dt with [1 -1] as the > differentiator. (Phase wrap-around at +/-pi and pre/deemphasis also has > been taken cared of). > > One of the main concerns not too sure about is the phase noise in the > system since it is running on a FPGA. > > In addition, there are some bin-based polyphase filters between the > input ADC and the FM Demod to make up the differences in their possible > sampling rates. I recall for a M/N integer fractional ratio, a > polyphase should be equivalent to a Upsampling-Downsampling filter with > the intermediate parts cancelled out mathematically. > > However, can this bin-based architecture able to hold out for the case > of the non-integer fractional steps? The gut feeling is a bit insecure > since there are Approximations involved to the resampling phases during > the process. Will this type of polyphase architecture generate extra > phase noises to the data that get propagated to the output noise? > > Also, are there any ways to help improve robustness of FM demodulation > against phase noise in general (ie. phase noise due to clock jitters > and uneven sampling rates on the FPGA and etc)? > > Finally, are there other common possible causes for the poor > performance that I missed? > > Any help is appreciated. Thanks in advance. >
What everyone has said so far, plus: Have you modeled this demodulation algorithm separate from the FPGA and looked for noise? I would be tempted to model this in SciLab, MatLab or other good simulation language, and see what the output looked like. If it passes through your simulation with flying colors, then you have an implementation problem. If it messes up in your simulation, then you have more tools at your disposal for finding where the noise is creeping in. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.html
Yip wrote:

> Hi All, >
-- snip --
> In addition, there are some bin-based polyphase filters between the > input ADC and the FM Demod to make up the differences in their possible > sampling rates. I recall for a M/N integer fractional ratio, a > polyphase should be equivalent to a Upsampling-Downsampling filter with > the intermediate parts cancelled out mathematically. > > However, can this bin-based architecture able to hold out for the case > of the non-integer fractional steps? The gut feeling is a bit insecure > since there are Approximations involved to the resampling phases during > the process. Will this type of polyphase architecture generate extra > phase noises to the data that get propagated to the output noise?
Replace your front end with a block that generates a pure sine wave, and 'demodulate' that. If it's not noisy, you've isolated your problem. If it is noisy, you know you don't have to worry about polyphase filtering (or at least _just_ the polyphase filtering).
> > Also, are there any ways to help improve robustness of FM demodulation > against phase noise in general (ie. phase noise due to clock jitters > and uneven sampling rates on the FPGA and etc)?
Get rid of the sampling jitters, of course! -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.html
Yip

Don't use PLL oscillators like the field programmable ones you can buy with 
a one day turnaround for sampling purposes. Instead use properly cut 
oscillators. I learnt that the hard way (they didn't teach you this stuff 
when I went to college). 100ps jitter at 10MHz is a sampling disaster of the 
order you're talking about.

Howard 


On 3 Dec 2006 17:39:30 -0800, "Yip" <yipkingsui@hotmail.com> wrote:


    (snipped)
>> >> [1 -1] as a differentiator is not good idea. The THD will be limited by >> the accuracy of the differentiator unless you employ a ridiculously high >> oversampling ratio. You should use a good FIR differentiator. > >The [1 -1] differentiator currently runs at ~1.5MHz sampling rate for a >currently 15kHz deviation signal (60% of a 25kHz = 100% deviation). Is >this considered a high or low oversampling ratio?
Hi Yip, If I understand the situation here, your "first difference" differentiator should be operating in its linear range. (The linear freq range is from zero hz to roughly Fs/10.) So this is good. However, that differentiator does amplify (somewhat) high frequency noise. Just for giggles, you might take a look at another differentiator at: http://www.elecdesign.com/Articles/Index.cfm?AD=1&ArticleID=13358 Good Luck, [-Rick-]