FMDemod, Phase noise and Polyphase

Thanks for the suggestions.

Unfortunately changing the differentiator doesn't seem affect much
towards this problem. The problem is still a high noise floor that is
inband..

However, I was able to confirm running the demod model by itself, or
even using the same ADC but run a much lower carrier frequency (4.5MHz
as opposed to 40.25MHz) both improves the SNR by a-lot (orders of
improvements). But the targetted input frequency range of 40.25MHz is
giving me the problems right now.

> Don't use PLL oscillators like the field programmable ones you can buy with
> a one day turnaround for sampling purposes. Instead use properly cut
> oscillators. I learnt that the hard way (they didn't teach you this stuff
> when I went to college). 100ps jitter at 10MHz is a sampling disaster of the
> order you're talking about.

This kind of freaks me out since I remember the oscillator really was a
next-day delivery type. I think it was 108MHz type and mentions a 50ppm
frequency tolerance. Is it good/bad? Is it possible to infer the clock
and sampling jitters from there?

What would be a reasonable overall ADC jitter amount for sampling
30~40MHz and 40~50MHz range to perform FM demodulaton?

Also, is there a way to model and simulate effects of sampling
distortions via a software model?

Thanks in advance.