baudrate dvb with cyclone

Hi guys,

   we have a ip working in FPGA StratixII using a reconfigurable pll to
generate the correct baud rate output for one DVBS modulator. We need
reduce cost and we decided migrate to device Altera cycloneII. The problem
is that cycloneII fpga there are no reconfigurable PLL. Its possible to
generate one counter to generate the output baudrate (1 to 35MSPS - each 1
Kilo symbol) from one input clock ? 
   It will work out if we look for an average baudrate ? 
   For example if we need 23MSPS, can we use the output with 1,84% of
1/(12,5MSPS) and 98,16% of (1/25MSPS) -- choose 12,5 and 25 because 50MHZ
its our hipothetical work frequency -- this will give us in average
24,7MSPS, but the symbol will not have the same period. Can we do this ?

Thanks in advantage
Phill