Forums

Boundary Scan Register - ADI BlackFin533

Started by Ed H. June 1, 2004
Hi everyone,

I'm new to this group. I'm doing an undergradued internship involving
DSP. Never worked with DSP before. I hope my questions (nor my poor
level of english) will upset anyone.

I have a ADI blackfin 533 EZKit. In order to accomplish my assignment
I need to know the content of the Boundary Scan register used by the
JTAG emulator.

Here's my question:
Does anyone know where can I find the Scan Path Position and
Definition for the BF533?

Up to now I've easily found the Scan Path Position and Definition for
the BlackFin535. I've just lookup 'boundary scan' with the HELP of
VisualDSP++ 3.5. I found Table C-3. Scan Path Position Definitions (in
the hardware Manual of the 535). But there's nothing similar in the
BF533 Hardware Manual... I don't understand why!

If for an obscure reason this information is non-public for the
BF533... is there any workaround? I need the same information than the
one in the previously mention Table C-3.

I'll post the same question to ADI support tonigh. 

Any hint or advice will be very appreciate. 

Ed H.
Are you looking for the bsdl file?  This contains the boundary scan bit
definitions.

PD


http://www.analog.com/processors/resources/designTools/bsdl.html

"Ed H." <geewazou@yahoo.ca> wrote in message
news:1124c3fd.0406011223.115816f@posting.google.com...
> Hi everyone, > > I'm new to this group. I'm doing an undergradued internship involving > DSP. Never worked with DSP before. I hope my questions (nor my poor > level of english) will upset anyone. > > I have a ADI blackfin 533 EZKit. In order to accomplish my assignment > I need to know the content of the Boundary Scan register used by the > JTAG emulator. > > Here's my question: > Does anyone know where can I find the Scan Path Position and > Definition for the BF533? > > Up to now I've easily found the Scan Path Position and Definition for > the BlackFin535. I've just lookup 'boundary scan' with the HELP of > VisualDSP++ 3.5. I found Table C-3. Scan Path Position Definitions (in > the hardware Manual of the 535). But there's nothing similar in the > BF533 Hardware Manual... I don't understand why! > > If for an obscure reason this information is non-public for the > BF533... is there any workaround? I need the same information than the > one in the previously mention Table C-3. > > I'll post the same question to ADI support tonigh. > > Any hint or advice will be very appreciate. > > Ed H.
Yeah thanx!!! That's exactly what I was looking for ... but maybe it's
not what I need...

I took the BSDL files from ADI website. Now I know more what I must
send to the TAP controler but still don&#8217;t know how.

For my undergradued intership, I must document and experiment the
procedure to load a program (in the internal memory of the DSP or
external flash memory) on a custom board thru the JTAG emulator in
order to avoid using an eeprom and eventually debug and do services
stuff.

I have a HPPCI JTAG emulator, an EZKit Blackfin 533 and eventually the
custom board (not done yet) design by another student (a master degree
project). As I request I should have access to the board schematic
soon. (I hope)

I have load some examples in the EZKit using the JTAG emulator.
Everything work fine. From ADI documentation I understand that I can
setup my session with the &#8216;VisualDSP Configurator&#8217; in
order to specify the TDO to TDI list of JTAG compliant device in the
JTAG chain access by the TAP port.

So if I start a session in VisualDSP++ set the configurator for
Device0=BF355 and plug the JTAG POD on a board with only a BF533 on
the JTAG chain (like the EZKit I think), will it works???

I think it will but the board will be complete in a few week so I need
the answer (or at least some hope) before trying it.


Now if the board is different, let&#8217;s say more than one BF533 and
another (non-ADI) device with a known boundary scan register on the
boundary scan path, I think I&#8217;m screwed&#8230; How can I tell
VisualDSP++ what is on the JTAG chain (scan path)?

Is there something more I can do with the linker, the  loader, a
library or directly the .DXE while still using the HPPCI pod?

From the 1149.1 Std, and some emulator brochure company, I should be
able to do a lot of  stuff (load internal memory, load the external
flash memory, &#8230;) with the JTAG POD and the rigth soft. Is there
any API available so I can access the  pod ? (like XJTAG offer with
their pod)

I want to ask ADI support but as you can see my interrogations are all
over the place. Don&#8217;t know what to ask for.


Any comment, hint or advice would be extremely useful 
Thanx in advance,

Mathieu McKinnon (who speak french) 

"KG7HF" <KG7HF@amsat.org> wrote in message news:<y6-dnW5lBYJplCDdRVn-uA@adelphia.com>...
> Are you looking for the bsdl file? This contains the boundary scan bit > definitions. > > PD > > > http://www.analog.com/processors/resources/designTools/bsdl.html > > "Ed H." <geewazou@yahoo.ca> wrote in message > news:1124c3fd.0406011223.115816f@posting.google.com... > > Hi everyone, > > > > I'm new to this group. I'm doing an undergradued internship involving > > DSP. Never worked with DSP before. I hope my questions (nor my poor > > level of english) will upset anyone. > > > > I have a ADI blackfin 533 EZKit. In order to accomplish my assignment > > I need to know the content of the Boundary Scan register used by the > > JTAG emulator. > > > > Here's my question: > > Does anyone know where can I find the Scan Path Position and > > Definition for the BF533? > > > > Up to now I've easily found the Scan Path Position and Definition for > > the BlackFin535. I've just lookup 'boundary scan' with the HELP of > > VisualDSP++ 3.5. I found Table C-3. Scan Path Position Definitions (in > > the hardware Manual of the 535). But there's nothing similar in the > > BF533 Hardware Manual... I don't understand why! > > > > If for an obscure reason this information is non-public for the > > BF533... is there any workaround? I need the same information than the > > one in the previously mention Table C-3. > > > > I'll post the same question to ADI support tonigh. > > > > Any hint or advice will be very appreciate. > > > > Ed H.
Yeah thanx! That's exactly what I was looking for... but maybe not
what I need...

I took the BSDL files from ADI website. Now I know more what I must
send to the TAP controler but still don't know how.

For my undergradued intership, I must document and experiment the
procedure to load a program (in the internal memory of the DSP or
external flash memory) on a custom board thru the JTAG emulator in
order to avoid using an eeprom and eventually debug and do services
stuff.

I have a HPPCI JTAG emulator, an EZKit Blackfin 533 and eventually the
custom board (not done yet) design by another student (a master degree
project). As I request I should have access to the board schematic
soon. (I hope)

I have load some examples in the EZKit using the JTAG emulator.
Everything work fine. From ADI documentation I understand that I can
setup my session with the 'VisualDSP Configurator' in order to specify
the TDO to TDI list of JTAG compliant device in the JTAG chain access
by the TAP port.

So if I start a session in VisualDSP++ set the configurator for
Device0=BF355 and plug the JTAG POD on a board with only a BF533 on
the JTAG chain (like the EZKit I think), will it works???

I think it will but the board will be complete in a few week so I need
the answer (or at least some hope) before trying it.


Now if the board is different, let's say more than one BF533 and
another (non-ADI) device with a known boundary scan register on the
boundary scan path, I think I'm screwed...

How can I tell VisualDSP++ what is on the JTAG chain (scan path)?

Is there something more I can do with the linker, the  loader, a
library or directly the .DXE while still using the HPPCI pod?

From the 1149.1 Std, and some emulator brochure company, I should be
able to do a lot of  stuff (load internal memory, program external
flash memory, so on...) with the JTAG POD and the rigth software. Is
there any API available so I can access the  pod ? (like XJTAG offer
with their pod)

I want to ask ADI support but as you can see my interrogations are all
over the place. Don't know what to ask for.

Visual Help file mention API for third party. Anyone have worked with
those??


Any comment, hint or advice would be extremely useful 
Thanx in advance,

Mathieu McKinnon (who speak french) 
 


"KG7HF" <KG7HF@amsat.org> wrote in message news:<y6-dnW5lBYJplCDdRVn-uA@adelphia.com>...
> Are you looking for the bsdl file? This contains the boundary scan bit > definitions. > > PD > > > http://www.analog.com/processors/resources/designTools/bsdl.html > > "Ed H." <geewazou@yahoo.ca> wrote in message > news:1124c3fd.0406011223.115816f@posting.google.com... > > Hi everyone, > > > > I'm new to this group. I'm doing an undergradued internship involving > > DSP. Never worked with DSP before. I hope my questions (nor my poor > > level of english) will upset anyone. > > > > I have a ADI blackfin 533 EZKit. In order to accomplish my assignment > > I need to know the content of the Boundary Scan register used by the > > JTAG emulator. > > > > Here's my question: > > Does anyone know where can I find the Scan Path Position and > > Definition for the BF533? > > > > Up to now I've easily found the Scan Path Position and Definition for > > the BlackFin535. I've just lookup 'boundary scan' with the HELP of > > VisualDSP++ 3.5. I found Table C-3. Scan Path Position Definitions (in > > the hardware Manual of the 535). But there's nothing similar in the > > BF533 Hardware Manual... I don't understand why! > > > > If for an obscure reason this information is non-public for the > > BF533... is there any workaround? I need the same information than the > > one in the previously mention Table C-3. > > > > I'll post the same question to ADI support tonigh. > > > > Any hint or advice will be very appreciate. > > > > Ed H.
Hi Ed,
See comments below:


"Ed H." <geewazou@yahoo.ca> wrote in message
news:1124c3fd.0406040713.74b98657@posting.google.com...
> Yeah thanx!!! That's exactly what I was looking for ... but maybe it's > not what I need... > > I took the BSDL files from ADI website. Now I know more what I must > send to the TAP controler but still don&#8217;t know how. > > For my undergradued intership, I must document and experiment the > procedure to load a program (in the internal memory of the DSP or > external flash memory) on a custom board thru the JTAG emulator in > order to avoid using an eeprom and eventually debug and do services > stuff.
You simply have to write the procedure to use VisaulDSP to load a program? This sounds fairly easy. Or, Q1. Are you asking that you have to write a piece of software that connects to the ADI emulator and downloads the program? A1. Much more diffictule, more than likely impossible without a huge time investment in reverse engineering the commands sent to the emulator over the PCI bus. I highly doubt ADI will offer any help with this. Q2. Are you saying you have to design the hardware and software which controls TCLK, TMS, and TDI to download the program, while using TDO to read back data? A2. Even more complicated. The internal registers used to perform debug and control are not public, only the implemented IEEE standard registers are public. ADI will probably offer no help.
> > I have a HPPCI JTAG emulator, an EZKit Blackfin 533 and eventually the > custom board (not done yet) design by another student (a master degree > project). As I request I should have access to the board schematic > soon. (I hope)
You mean the HPPCI schematic? I don't think ADI will give that out.
> > I have load some examples in the EZKit using the JTAG emulator. > Everything work fine. From ADI documentation I understand that I can > setup my session with the &#8216;VisualDSP Configurator&#8217; in > order to specify the TDO to TDI list of JTAG compliant device in the > JTAG chain access by the TAP port.
Yes, very true. You can specify both ADI and non-ADI jtag parts in the configurator, you configure non-ADI, and non-Blackfin (such as sharc) as "unknown" devices. You need to know the IR width size of the other jtag parts.
> > So if I start a session in VisualDSP++ set the configurator for > Device0=BF355 and plug the JTAG POD on a board with only a BF533 on > the JTAG chain (like the EZKit I think), will it works???
I would say so, but I don't understand the question.
> > I think it will but the board will be complete in a few week so I need > the answer (or at least some hope) before trying it. > > > Now if the board is different, let&#8217;s say more than one BF533 and > another (non-ADI) device with a known boundary scan register on the > boundary scan path, I think I&#8217;m screwed&#8230; How can I tell > VisualDSP++ what is on the JTAG chain (scan path)?
easy, specify the number of BF533's in the configurator. The important thing is to know where the BF533's are in the TDI->TDO path, and how many bits the IR (instruction register) is in the unknown device. For example, if you had two BF533's and one other non-ADI device in a configuration such as TDI -> BF533 -> fpga -> BF533 ->TDO you would list it in the configurator as: Device0 = BF533 Device1 = unknown Device2 = BF533
> > Is there something more I can do with the linker, the loader, a > library or directly the .DXE while still using the HPPCI pod?
You mean without VisualDSP? I don't understand.
> > From the 1149.1 Std, and some emulator brochure company, I should be > able to do a lot of stuff (load internal memory, load the external > flash memory, &#8230;) with the JTAG POD and the rigth soft. Is there > any API available so I can access the pod ? (like XJTAG offer with > their pod)
Not that I know of, and I doubt ADI will offer any insight on how to do that.
> > I want to ask ADI support but as you can see my interrogations are all > over the place. Don&#8217;t know what to ask for. > > > Any comment, hint or advice would be extremely useful > Thanx in advance, > > Mathieu McKinnon (who speak french)
I don't speak French, but my wife is fluent. Best Regards, PD.
> > "KG7HF" <KG7HF@amsat.org> wrote in message
news:<y6-dnW5lBYJplCDdRVn-uA@adelphia.com>...
> > Are you looking for the bsdl file? This contains the boundary scan bit > > definitions. > > > > PD > > > > > > http://www.analog.com/processors/resources/designTools/bsdl.html > > > > "Ed H." <geewazou@yahoo.ca> wrote in message > > news:1124c3fd.0406011223.115816f@posting.google.com... > > > Hi everyone, > > > > > > I'm new to this group. I'm doing an undergradued internship involving > > > DSP. Never worked with DSP before. I hope my questions (nor my poor > > > level of english) will upset anyone. > > > > > > I have a ADI blackfin 533 EZKit. In order to accomplish my assignment > > > I need to know the content of the Boundary Scan register used by the > > > JTAG emulator. > > > > > > Here's my question: > > > Does anyone know where can I find the Scan Path Position and > > > Definition for the BF533? > > > > > > Up to now I've easily found the Scan Path Position and Definition for > > > the BlackFin535. I've just lookup 'boundary scan' with the HELP of > > > VisualDSP++ 3.5. I found Table C-3. Scan Path Position Definitions (in > > > the hardware Manual of the 535). But there's nothing similar in the > > > BF533 Hardware Manual... I don't understand why! > > > > > > If for an obscure reason this information is non-public for the > > > BF533... is there any workaround? I need the same information than the > > > one in the previously mention Table C-3. > > > > > > I'll post the same question to ADI support tonigh. > > > > > > Any hint or advice will be very appreciate. > > > > > > Ed H.
Hi PD,
you are making my life less a nigthmare... I add some details to my
question

"KG7HF" <KG7HF@amsat.org> wrote in message news:<erudnYiZcfTLjVzdRVn-vA@adelphia.com>...
> Hi Ed, > See comments below: > > > "Ed H." <geewazou@yahoo.ca> wrote in message > news:1124c3fd.0406040713.74b98657@posting.google.com... > > Yeah thanx!!! That's exactly what I was looking for ... but maybe it's > > not what I need... > > > > I took the BSDL files from ADI website. Now I know more what I must > > send to the TAP controler but still don&#8217;t know how. > > > > For my undergradued intership, I must document and experiment the > > procedure to load a program (in the internal memory of the DSP or > > external flash memory) on a custom board thru the JTAG emulator in > > order to avoid using an eeprom and eventually debug and do services > > stuff. > You simply have to write the procedure to use VisaulDSP to load a program? > This sounds fairly easy. > Or, > Q1. Are you asking that you have to write a piece of software that connects > to the ADI emulator and downloads the program? > A1. Much more diffictule, more than likely impossible without a huge time > investment in reverse engineering the commands sent to the emulator over the > PCI bus. I highly doubt ADI will offer any help with this. > > Q2. Are you saying you have to design the hardware and software which > controls TCLK, TMS, and TDI to download the program, while using TDO to read > back data? > A2. Even more complicated. The internal registers used to perform debug > and control are not public, only the implemented IEEE standard registers are > public. ADI will probably offer no help.
Here you confirm all my judgment. I'm not alone anymore! I've been ask Q1, but I wonder if my supervisor is fully aware of what he is asking. At first he said all I need to do was loading a ADI DSP on a board one of is other student designed using the JTAG header. This required no extra soft... just a plain VisualDSP++ build (with the proper configurator) and a EE-68 compliant board. Right? As I told I never really worked with VisualDSP. What kind of license do I need? Don't you think making a slow (like serial port)"hardware and software which controls TCLK, TMS, and TDI to download the program, while using TDO to read back data" is more easy than "write a piece of software that connects to the ADI emulator and downloads the program"? Of course without the option of Debug wich is whole new world of trouble.
> > > > > I have a HPPCI JTAG emulator, an EZKit Blackfin 533 and eventually the > > custom board (not done yet) design by another student (a master degree > > project). As I request I should have access to the board schematic > > soon. (I hope) > You mean the HPPCI schematic? I don't think ADI will give that out.
No I meant the schematic of the other student board. Up to now nobody here is able to tell me what is on the JTAG scan path of that board beside one BF355 (nor what is on that board).
> > > > > I have load some examples in the EZKit using the JTAG emulator. > > Everything work fine. From ADI documentation I understand that I can > > setup my session with the &#8216;VisualDSP Configurator&#8217; in > > order to specify the TDO to TDI list of JTAG compliant device in the > > JTAG chain access by the TAP port. > Yes, very true. You can specify both ADI and non-ADI jtag parts in the > configurator, you configure non-ADI, and non-Blackfin (such as sharc) as > "unknown" devices. You need to know the IR width size of the other jtag > parts. > > > > > So if I start a session in VisualDSP++ set the configurator for > > Device0=BF355 and plug the JTAG POD on a board with only a BF533 on > > the JTAG chain (like the EZKit I think), will it works??? > I would say so, but I don't understand the question.
The main idea here (altough it's clearly unclear) is: On a EZ-Kit is there somehing between the 13-pins JTAG Header and the DSP? Because on the schematics of the EZKit manual, the wire of the header are call EMULATOR_TMS, EMULATOR_TCK, and so on while on the DSP side is TMS, TCK,... If no everything should work fine like the EZKit
> > > > > I think it will but the board will be complete in a few week so I need > > the answer (or at least some hope) before trying it. > > > > > > Now if the board is different, let&#8217;s say more than one BF533 and > > another (non-ADI) device with a known boundary scan register on the > > boundary scan path, I think I&#8217;m screwed&#8230; How can I tell > > VisualDSP++ what is on the JTAG chain (scan path)? > easy, specify the number of BF533's in the configurator. The important > thing is to know where the BF533's are in the TDI->TDO path, and how many > bits the IR (instruction register) is in the unknown device. For example, > if you had two BF533's and one other non-ADI device in a configuration such > as TDI -> BF533 -> fpga -> BF533 ->TDO you would list it in the configurator > as: > Device0 = BF533 > Device1 = unknown > Device2 = BF533 > > > > > > Is there something more I can do with the linker, the loader, a > > library or directly the .DXE while still using the HPPCI pod? > You mean without VisualDSP? I don't understand.
Sound like stupid now but I tough about modifying .DXE manually (assuming that this is what the configurator do). Than programming a loader that use the ADI JTAG pod. In the end it's the same as using Visual without using it (and wasting a lot of time along the way).
> > > > > From the 1149.1 Std, and some emulator brochure company, I should be > > able to do a lot of stuff (load internal memory, load the external > > flash memory, &#8230;) with the JTAG POD and the rigth soft. Is there > > any API available so I can access the pod ? (like XJTAG offer with > > their pod) > Not that I know of, and I doubt ADI will offer any insight on how to do > that.
The Visual DSP mention COM API if you seach 'API ICE'. But they don't say how much($$$) or for what use.
> > > > > I want to ask ADI support but as you can see my interrogations are all > > over the place. Don&#8217;t know what to ask for. > > > > > > Any comment, hint or advice would be extremely useful > > Thanx in advance, > > > > Mathieu McKinnon (who speak french) > I don't speak French, but my wife is fluent. > > > Best Regards, > PD. > > > > > > > "KG7HF" <KG7HF@amsat.org> wrote in message > news:<y6-dnW5lBYJplCDdRVn-uA@adelphia.com>... > > > Are you looking for the bsdl file? This contains the boundary scan bit > > > definitions. > > > > > > PD > > > > > > > > > http://www.analog.com/processors/resources/designTools/bsdl.html > > > > > > "Ed H." <geewazou@yahoo.ca> wrote in message > > > news:1124c3fd.0406011223.115816f@posting.google.com... > > > > Hi everyone, > > > > > > > > I'm new to this group. I'm doing an undergradued internship involving > > > > DSP. Never worked with DSP before. I hope my questions (nor my poor > > > > level of english) will upset anyone. > > > > > > > > I have a ADI blackfin 533 EZKit. In order to accomplish my assignment > > > > I need to know the content of the Boundary Scan register used by the > > > > JTAG emulator. > > > > > > > > Here's my question: > > > > Does anyone know where can I find the Scan Path Position and > > > > Definition for the BF533? > > > > > > > > Up to now I've easily found the Scan Path Position and Definition for > > > > the BlackFin535. I've just lookup 'boundary scan' with the HELP of > > > > VisualDSP++ 3.5. I found Table C-3. Scan Path Position Definitions (in > > > > the hardware Manual of the 535). But there's nothing similar in the > > > > BF533 Hardware Manual... I don't understand why! > > > > > > > > If for an obscure reason this information is non-public for the > > > > BF533... is there any workaround? I need the same information than the > > > > one in the previously mention Table C-3. > > > > > > > > I'll post the same question to ADI support tonigh. > > > > > > > > Any hint or advice will be very appreciate. > > > > > > > > Ed H.
"Ed H." <geewazou@yahoo.ca> wrote in message
news:1124c3fd.0406070542.1109fe21@posting.google.com...
> Hi PD, > you are making my life less a nigthmare... I add some details to my > question > > "KG7HF" <KG7HF@amsat.org> wrote in message
news:<erudnYiZcfTLjVzdRVn-vA@adelphia.com>...
> > Hi Ed, > > See comments below: > > > > > > "Ed H." <geewazou@yahoo.ca> wrote in message > > news:1124c3fd.0406040713.74b98657@posting.google.com... > > > Yeah thanx!!! That's exactly what I was looking for ... but maybe it's > > > not what I need... > > > > > > I took the BSDL files from ADI website. Now I know more what I must > > > send to the TAP controler but still don&#8217;t know how. > > > > > > For my undergradued intership, I must document and experiment the > > > procedure to load a program (in the internal memory of the DSP or > > > external flash memory) on a custom board thru the JTAG emulator in > > > order to avoid using an eeprom and eventually debug and do services > > > stuff. > > You simply have to write the procedure to use VisaulDSP to load a
program?
> > This sounds fairly easy. > > Or, > > Q1. Are you asking that you have to write a piece of software that
connects
> > to the ADI emulator and downloads the program? > > A1. Much more diffictule, more than likely impossible without a huge
time
> > investment in reverse engineering the commands sent to the emulator over
the
> > PCI bus. I highly doubt ADI will offer any help with this. > > > > Q2. Are you saying you have to design the hardware and software which > > controls TCLK, TMS, and TDI to download the program, while using TDO to
read
> > back data? > > A2. Even more complicated. The internal registers used to perform
debug
> > and control are not public, only the implemented IEEE standard registers
are
> > public. ADI will probably offer no help. > > Here you confirm all my judgment. I'm not alone anymore! > > I've been ask Q1, but I wonder if my supervisor is fully aware of what > he is asking. At first he said all I need to do was loading a ADI DSP > on a board one of is other student designed using the JTAG header. > This required no extra soft... just a plain VisualDSP++ build (with > the proper configurator) and a EE-68 compliant board. Right? As I told > I never really worked with VisualDSP. What kind of license do I need?
You are correct, all that is necessary is an EE-68 complient board, and a licensed version of VisualDSP that you can use with your PCI emulator. I'm not sure what type of license is required, probably a full license.
> > Don't you think making a slow (like serial port)"hardware and software > which controls TCLK, TMS, and TDI to download the program, while using > TDO to read back data" is more easy than "write a piece of software > that connects to the ADI emulator and downloads the program"?
I think they are about the same level of difficulty. In either case, you will have to reverse engineer something. In one case, you have to reverse engineer the PCI read/writes to the ADI controller. In the other case, you have to reverse engineer the JTAG scan signals and figure out how a download is performed.
> ... Of course without the option of Debug wich is whole new world of
trouble. Debug is one thing, but to download the program, there are special internal JTAG registers and commands that are not public. These JTAG registers and commands actaully allow you to download/read/write memory. Without knowledge of these JTAG commands and registers, makes it really difficult.
> > > > > > > > > I have a HPPCI JTAG emulator, an EZKit Blackfin 533 and eventually the > > > custom board (not done yet) design by another student (a master degree > > > project). As I request I should have access to the board schematic > > > soon. (I hope) > > You mean the HPPCI schematic? I don't think ADI will give that out. > > No I meant the schematic of the other student board. Up to now nobody > here is able to tell me what is on the JTAG scan path of that board > beside one BF355 (nor what is on that board). > > > > > > > > > I have load some examples in the EZKit using the JTAG emulator. > > > Everything work fine. From ADI documentation I understand that I can > > > setup my session with the &#8216;VisualDSP Configurator&#8217; in > > > order to specify the TDO to TDI list of JTAG compliant device in the > > > JTAG chain access by the TAP port. > > Yes, very true. You can specify both ADI and non-ADI jtag parts in the > > configurator, you configure non-ADI, and non-Blackfin (such as sharc) as > > "unknown" devices. You need to know the IR width size of the other jtag > > parts. > > > > > > > > So if I start a session in VisualDSP++ set the configurator for > > > Device0=BF355 and plug the JTAG POD on a board with only a BF533 on > > > the JTAG chain (like the EZKit I think), will it works??? > > I would say so, but I don't understand the question. > > The main idea here (altough it's clearly unclear) is: > On a EZ-Kit is there somehing between the 13-pins JTAG Header and the > DSP? > Because on the schematics of the EZKit manual, the wire of the header > are call EMULATOR_TMS, EMULATOR_TCK, and so on while on the DSP side > is TMS, TCK,... > If no everything should work fine like the EZKit
There is only one device on the EZ-Kit board, the signals may be marked differently because of the onboard USB debug agent with is also a JTAG controller of sorts. I believe these signals provide a way to switch between the PCI JTAG emulator, and the built in JTAG emulator.
> > > > > > > > > I think it will but the board will be complete in a few week so I need > > > the answer (or at least some hope) before trying it. > > > > > > > > > Now if the board is different, let&#8217;s say more than one BF533 and > > > another (non-ADI) device with a known boundary scan register on the > > > boundary scan path, I think I&#8217;m screwed&#8230; How can I tell > > > VisualDSP++ what is on the JTAG chain (scan path)? > > easy, specify the number of BF533's in the configurator. The important > > thing is to know where the BF533's are in the TDI->TDO path, and how
many
> > bits the IR (instruction register) is in the unknown device. For
example,
> > if you had two BF533's and one other non-ADI device in a configuration
such
> > as TDI -> BF533 -> fpga -> BF533 ->TDO you would list it in the
configurator
> > as: > > Device0 = BF533 > > Device1 = unknown > > Device2 = BF533 > > > > > > > > > > Is there something more I can do with the linker, the loader, a > > > library or directly the .DXE while still using the HPPCI pod? > > You mean without VisualDSP? I don't understand. > > Sound like stupid now but I tough about modifying .DXE manually > (assuming that this is what the configurator do). Than programming a > loader that use the > ADI JTAG pod. In the end it's the same as using Visual without using > it (and wasting a lot of time along the way).
I'm not sure I understand this yet. The configurator doesn't modify the DXE. The configurator only describes the scan path to the emulator so the emulator knows what devices are in the scan chain, and how large their IR register is. A DXE is parsed, the various memory sections are then sent to the emulator to download. This is vastly different than what an LDR (loader file) is. A loader file contains no debug information, it is strictly meant to be programmed into a memory device such as ROM or FLASH.
> > > > > > > > > From the 1149.1 Std, and some emulator brochure company, I should be > > > able to do a lot of stuff (load internal memory, load the external > > > flash memory, &#8230;) with the JTAG POD and the rigth soft. Is there > > > any API available so I can access the pod ? (like XJTAG offer with > > > their pod) > > Not that I know of, and I doubt ADI will offer any insight on how to do > > that. > > The Visual DSP mention COM API if you seach 'API ICE'. But they don't > say how much($$$) or for what use.
There is an automation API which you can use to do almost any debug functions. Look up the VisualDSP Automation API, maybe that will do what you want?
> > > > > > > > > I want to ask ADI support but as you can see my interrogations are all > > > over the place. Don&#8217;t know what to ask for. > > > > > > > > > Any comment, hint or advice would be extremely useful > > > Thanx in advance, > > > > > > Mathieu McKinnon (who speak french) > > I don't speak French, but my wife is fluent. > > > > > > Best Regards, > > PD. > > > > > > > > > > > > "KG7HF" <KG7HF@amsat.org> wrote in message > > news:<y6-dnW5lBYJplCDdRVn-uA@adelphia.com>... > > > > Are you looking for the bsdl file? This contains the boundary scan
bit
> > > > definitions. > > > > > > > > PD > > > > > > > > > > > > http://www.analog.com/processors/resources/designTools/bsdl.html > > > > > > > > "Ed H." <geewazou@yahoo.ca> wrote in message > > > > news:1124c3fd.0406011223.115816f@posting.google.com... > > > > > Hi everyone, > > > > > > > > > > I'm new to this group. I'm doing an undergradued internship
involving
> > > > > DSP. Never worked with DSP before. I hope my questions (nor my
poor
> > > > > level of english) will upset anyone. > > > > > > > > > > I have a ADI blackfin 533 EZKit. In order to accomplish my
assignment
> > > > > I need to know the content of the Boundary Scan register used by
the
> > > > > JTAG emulator. > > > > > > > > > > Here's my question: > > > > > Does anyone know where can I find the Scan Path Position and > > > > > Definition for the BF533? > > > > > > > > > > Up to now I've easily found the Scan Path Position and Definition
for
> > > > > the BlackFin535. I've just lookup 'boundary scan' with the HELP of > > > > > VisualDSP++ 3.5. I found Table C-3. Scan Path Position Definitions
(in
> > > > > the hardware Manual of the 535). But there's nothing similar in
the
> > > > > BF533 Hardware Manual... I don't understand why! > > > > > > > > > > If for an obscure reason this information is non-public for the > > > > > BF533... is there any workaround? I need the same information than
the
> > > > > one in the previously mention Table C-3. > > > > > > > > > > I'll post the same question to ADI support tonigh. > > > > > > > > > > Any hint or advice will be very appreciate. > > > > > > > > > > Ed H.