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Parallel Decimation Filter Implementation?

Started by Phil April 18, 2007
Hi,

I'm hoping that someone out there may be able to help me solve this
problem.

I'm trying to create a decimate by 2 filter that will have 4 parallel
inputs and 2 outputs.  The reason for doing this is that I am
receiving data into my FPGA at 4 times the clock FPGAs clock rate.
This is being done by bringing in 4 samples per clock.

I was thinking of using a polyphase filter, but this does not seem
feasible for my 4-in 2-out scenario.  I think this has become a
parallelism problem.  I'm trying to figure out an implementation that
works, but if anyone has some advice for my, I would really appreciate
it.

Thanks in advance for any help.

Phil

Phil wrote:
> Hi, > > I'm hoping that someone out there may be able to help me solve this > problem. > > I'm trying to create a decimate by 2 filter that will have 4 parallel > inputs and 2 outputs. The reason for doing this is that I am > receiving data into my FPGA at 4 times the clock FPGAs clock rate. > This is being done by bringing in 4 samples per clock. > > I was thinking of using a polyphase filter, but this does not seem > feasible for my 4-in 2-out scenario. I think this has become a > parallelism problem. I'm trying to figure out an implementation that > works, but if anyone has some advice for my, I would really appreciate > it. > > Thanks in advance for any help. > > Phil
It turns out that I was being dumb when looking at this implementation. Instead of the line-up that I mentioned below, I will be using a parallel NCO for downconverting the signal and then some half band filters for bandlimiting and downsampling. This is much less probelmatic and I think it reduces the complexity of my design. Phil