Forums

FFT Rounding error?

Started by Andrew Holme May 12, 2007
On May 14, 6:29 am, MooseFET <kensm...@rahul.net> wrote:
> On May 14, 2:15 am, m...@sushi.com wrote:> On May 13, 4:38 pm, MooseFET <kensm...@rahul.net> wrote: > > [.... windowed FFT in real world ...] > > > > That doesn't always cut it. Windowing creates its own artifacts. It > > > spreads signals into the the channels beside their true frequency. > > > You also really need to remove the DC before you window. If you > > > don't, the windowing raises the whole spectrum. > > > Yes, you need to pick the right window. That is, do you want amplitude > > accuracy, frequency accuracy, etc. > > What if I want both? Fitting a sine wave doesn't mess with either. > Yes it uses more CPU time but CPU time is cheap these days. > > > > > > > In some applications, you alter the rate of sampling to make the > > > > sampling synchronous to the signal. It's not all that hard, i.e. you > > > > just pull a crystal with a varactor. > > > > Have you done this? I found that people who say things aren't hard > > > have often not tried it. I pulled an SRS generator's clock to force > > > it onto the exact needed frequency once. One of the problems was that > > > any circuit that let me pull the crystal also added noise to the > > > crystal's frequency. In the end, I found a way that allowed a very > > > limited range. > > > Pulling the crystal was done in digital video recorders. [The usual > > signal flow is 4x over sampling, then create I and Q channel). Have I > > personally done this? No, I was working on a project where the > > consultant had done this elsewhere, but the project got canceled. I > > have done the scheme where the sample rate is controlled by a DPLL. We > > did this on a (don't laugh) 2400bps modem design. So the sample rate > > was tweaked to match the signal, but not by pulling the crysta. > > None of those could be considered a low noise situation. When you are > working with a noisy signal, the added noise of the crystal pulling > circuit doesn't matter. The DPLL method makes some interesting spikes > in the spectrum that come and go depending on a lot of factors. > > The output of a DPLL has a phase jitter caused by the fact that the > output must either switch on this edge or the next. The this vs the > next timing shake and the slope of a low frequency signal makes a > small artifact waveform. > > [....] > > > > > B&K made/makes a signal source with a 10MHz output on the back so that > > > > you can synthesize a clock for sampling that is synchronous to the > > > > audio test signal. > > > > Do you know the number? I generally use SRS stuff when I need low > > > noise signals. > > > I think it was the B&K 1049. It's only good to -96db, which was fine > > in the day. > > Closer to twice that would be good.
I often wonder how Crystal tests their ADCs? Perhaps an off the shelf function generator and passive filters.
On May 13, 4:17 pm, MooseFET <kensm...@rahul.net> wrote:
> On May 13, 11:34 am, "John E. Hadstate" <jh113...@hotmail.com> wrote: > > > "redbelly" <redbell...@yahoo.com> wrote in message > > >news:1179071750.419150.115650@w5g2000hsg.googlegroups.com... > > > > Either a window function, or as somebody else suggested > > > removing the > > > "ramp" in the data (get the best-fit line and subtract it > > > from the > > > data). Either way removes the artificial discontinuity. > > > Not true. Subtracting a best-fit line is not likely to > > remove the discontinuity. > > You are right. Don't take out the best fit line unless you are fairly > sure the problem is a simple drift. For a straight line drift, the > best fit line works well. > > In most cases, just using the difference between the first and last > sample works better than the best fit.
Good point. Yes, just using the best fit could still leave a discontinuity there. Then there is the question of discontinuities in the slope and in the second derivitive. Not as bad as a discontinuity in the function itself, but the windowing can take care of those as well. Mark
On May 14, 2:28 pm, m...@sushi.com wrote:
> On May 14, 6:29 am, MooseFET <kensm...@rahul.net> wrote: > > > > > On May 14, 2:15 am, m...@sushi.com wrote:> On May 13, 4:38 pm, MooseFET <kensm...@rahul.net> wrote: > > > [.... windowed FFT in real world ...] > > > > > That doesn't always cut it. Windowing creates its own artifacts. It > > > > spreads signals into the the channels beside their true frequency. > > > > You also really need to remove the DC before you window. If you > > > > don't, the windowing raises the whole spectrum. > > > > Yes, you need to pick the right window. That is, do you want amplitude > > > accuracy, frequency accuracy, etc. > > > What if I want both? Fitting a sine wave doesn't mess with either. > > Yes it uses more CPU time but CPU time is cheap these days. > > > > > > In some applications, you alter the rate of sampling to make the > > > > > sampling synchronous to the signal. It's not all that hard, i.e. you > > > > > just pull a crystal with a varactor. > > > > > Have you done this? I found that people who say things aren't hard > > > > have often not tried it. I pulled an SRS generator's clock to force > > > > it onto the exact needed frequency once. One of the problems was that > > > > any circuit that let me pull the crystal also added noise to the > > > > crystal's frequency. In the end, I found a way that allowed a very > > > > limited range. > > > > Pulling the crystal was done in digital video recorders. [The usual > > > signal flow is 4x over sampling, then create I and Q channel). Have I > > > personally done this? No, I was working on a project where the > > > consultant had done this elsewhere, but the project got canceled. I > > > have done the scheme where the sample rate is controlled by a DPLL. We > > > did this on a (don't laugh) 2400bps modem design. So the sample rate > > > was tweaked to match the signal, but not by pulling the crysta. > > > None of those could be considered a low noise situation. When you are > > working with a noisy signal, the added noise of the crystal pulling > > circuit doesn't matter. The DPLL method makes some interesting spikes > > in the spectrum that come and go depending on a lot of factors. > > > The output of a DPLL has a phase jitter caused by the fact that the > > output must either switch on this edge or the next. The this vs the > > next timing shake and the slope of a low frequency signal makes a > > small artifact waveform. > > > [....] > > > > > > B&K made/makes a signal source with a 10MHz output on the back so that > > > > > you can synthesize a clock for sampling that is synchronous to the > > > > > audio test signal. > > > > > Do you know the number? I generally use SRS stuff when I need low > > > > noise signals. > > > > I think it was the B&K 1049. It's only good to -96db, which was fine > > > in the day. > > > Closer to twice that would be good. > > I often wonder how Crystal tests their ADCs? Perhaps an off the shelf > function generator and passive filters.
There is a nice version of the Wein bridge oscillator that often gets used for this. There are two op-amps in the circuit and both of them are inverting. This removes the effects of common mode changes. The gain control is done either with a light controlled resistor or a couple of thermistors. It takes quite a while for the amplitude to settle but the noise and distortion values come out very good.
On May 14, 3:07 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> John Popelish wrote: > > glen herrmannsfeldt wrote: > > (snip regarding FFT and periodicity) > > >> I wouldn't call it a limitation, though, but fundamental, yes. > > Okay. It is a fundamental 'feature". ;-) > > I will agree with that. > > There is an old saying I can't quite remember about using a > wrench to pound in nails when you can't find the hammer.
"When the only tool you have is a hammer, everything looks like a nail".
MooseFET wrote:

(snip)

>>There is an old saying I can't quite remember about using a >>wrench to pound in nails when you can't find the hammer.
> "When the only tool you have is a hammer, everything looks like a > nail".
Yes, but I thought there was another one, but I suppose that works, too. -- glen
On May 14, 6:42 pm, MooseFET <kensm...@rahul.net> wrote:
> On May 14, 2:28 pm, m...@sushi.com wrote: > > > > > On May 14, 6:29 am, MooseFET <kensm...@rahul.net> wrote: > > > > On May 14, 2:15 am, m...@sushi.com wrote:> On May 13, 4:38 pm, MooseFET <kensm...@rahul.net> wrote: > > > > [.... windowed FFT in real world ...] > > > > > > That doesn't always cut it. Windowing creates its own artifacts. It > > > > > spreads signals into the the channels beside their true frequency. > > > > > You also really need to remove the DC before you window. If you > > > > > don't, the windowing raises the whole spectrum. > > > > > Yes, you need to pick the right window. That is, do you want amplitude > > > > accuracy, frequency accuracy, etc. > > > > What if I want both? Fitting a sine wave doesn't mess with either. > > > Yes it uses more CPU time but CPU time is cheap these days. > > > > > > > In some applications, you alter the rate of sampling to make the > > > > > > sampling synchronous to the signal. It's not all that hard, i.e. you > > > > > > just pull a crystal with a varactor. > > > > > > Have you done this? I found that people who say things aren't hard > > > > > have often not tried it. I pulled an SRS generator's clock to force > > > > > it onto the exact needed frequency once. One of the problems was that > > > > > any circuit that let me pull the crystal also added noise to the > > > > > crystal's frequency. In the end, I found a way that allowed a very > > > > > limited range. > > > > > Pulling the crystal was done in digital video recorders. [The usual > > > > signal flow is 4x over sampling, then create I and Q channel). Have I > > > > personally done this? No, I was working on a project where the > > > > consultant had done this elsewhere, but the project got canceled. I > > > > have done the scheme where the sample rate is controlled by a DPLL. We > > > > did this on a (don't laugh) 2400bps modem design. So the sample rate > > > > was tweaked to match the signal, but not by pulling the crysta. > > > > None of those could be considered a low noise situation. When you are > > > working with a noisy signal, the added noise of the crystal pulling > > > circuit doesn't matter. The DPLL method makes some interesting spikes > > > in the spectrum that come and go depending on a lot of factors. > > > > The output of a DPLL has a phase jitter caused by the fact that the > > > output must either switch on this edge or the next. The this vs the > > > next timing shake and the slope of a low frequency signal makes a > > > small artifact waveform. > > > > [....] > > > > > > > B&K made/makes a signal source with a 10MHz output on the back so that > > > > > > you can synthesize a clock for sampling that is synchronous to the > > > > > > audio test signal. > > > > > > Do you know the number? I generally use SRS stuff when I need low > > > > > noise signals. > > > > > I think it was the B&K 1049. It's only good to -96db, which was fine > > > > in the day. > > > > Closer to twice that would be good. > > > I often wonder how Crystal tests their ADCs? Perhaps an off the shelf > > function generator and passive filters. > > There is a nice version of the Wein bridge oscillator that often gets > used for this. There are two op-amps in the circuit and both of them > are inverting. This removes the effects of common mode changes. The > gain control is done either with a light controlled resistor or a > couple of thermistors. It takes quite a while for the amplitude to > settle but the noise and distortion values come out very good.
I have a HP 8903B, which is a decent source. I'm not sure you could roll something together that is better. I remember building the Wein bridge oscillator in school. We used a jfet for the gain control.
MooseFET wrote:
> > On May 14, 3:07 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > > John Popelish wrote: > > > glen herrmannsfeldt wrote: > > > > (snip regarding FFT and periodicity) > > > > >> I wouldn't call it a limitation, though, but fundamental, yes. > > > Okay. It is a fundamental 'feature". ;-) > > > > I will agree with that. > > > > There is an old saying I can't quite remember about using a > > wrench to pound in nails when you can't find the hammer. > > "When the only tool you have is a hammer, everything looks like a > nail".
When the only tool you have is a claw hammer, everything looks like a bent nail. ;-) -- Service to my country? Been there, Done that, and I've got my DD214 to prove it. Member of DAV #85. Michael A. Terrell Central Florida
On May 14, 8:39 pm, m...@sushi.com wrote:
> On May 14, 6:42 pm, MooseFET <kensm...@rahul.net> wrote: > > > > > On May 14, 2:28 pm, m...@sushi.com wrote: > > > > On May 14, 6:29 am, MooseFET <kensm...@rahul.net> wrote: > > > > > On May 14, 2:15 am, m...@sushi.com wrote:> On May 13, 4:38 pm, MooseFET <kensm...@rahul.net> wrote: > > > > > [.... windowed FFT in real world ...] > > > > > > > That doesn't always cut it. Windowing creates its own artifacts. It > > > > > > spreads signals into the the channels beside their true frequency. > > > > > > You also really need to remove the DC before you window. If you > > > > > > don't, the windowing raises the whole spectrum. > > > > > > Yes, you need to pick the right window. That is, do you want amplitude > > > > > accuracy, frequency accuracy, etc. > > > > > What if I want both? Fitting a sine wave doesn't mess with either. > > > > Yes it uses more CPU time but CPU time is cheap these days. > > > > > > > > In some applications, you alter the rate of sampling to make the > > > > > > > sampling synchronous to the signal. It's not all that hard, i.e. you > > > > > > > just pull a crystal with a varactor. > > > > > > > Have you done this? I found that people who say things aren't hard > > > > > > have often not tried it. I pulled an SRS generator's clock to force > > > > > > it onto the exact needed frequency once. One of the problems was that > > > > > > any circuit that let me pull the crystal also added noise to the > > > > > > crystal's frequency. In the end, I found a way that allowed a very > > > > > > limited range. > > > > > > Pulling the crystal was done in digital video recorders. [The usual > > > > > signal flow is 4x over sampling, then create I and Q channel). Have I > > > > > personally done this? No, I was working on a project where the > > > > > consultant had done this elsewhere, but the project got canceled. I > > > > > have done the scheme where the sample rate is controlled by a DPLL. We > > > > > did this on a (don't laugh) 2400bps modem design. So the sample rate > > > > > was tweaked to match the signal, but not by pulling the crysta. > > > > > None of those could be considered a low noise situation. When you are > > > > working with a noisy signal, the added noise of the crystal pulling > > > > circuit doesn't matter. The DPLL method makes some interesting spikes > > > > in the spectrum that come and go depending on a lot of factors. > > > > > The output of a DPLL has a phase jitter caused by the fact that the > > > > output must either switch on this edge or the next. The this vs the > > > > next timing shake and the slope of a low frequency signal makes a > > > > small artifact waveform. > > > > > [....] > > > > > > > > B&K made/makes a signal source with a 10MHz output on the back so that > > > > > > > you can synthesize a clock for sampling that is synchronous to the > > > > > > > audio test signal. > > > > > > > Do you know the number? I generally use SRS stuff when I need low > > > > > > noise signals. > > > > > > I think it was the B&K 1049. It's only good to -96db, which was fine > > > > > in the day. > > > > > Closer to twice that would be good. > > > > I often wonder how Crystal tests their ADCs? Perhaps an off the shelf > > > function generator and passive filters. > > > There is a nice version of the Wein bridge oscillator that often gets > > used for this. There are two op-amps in the circuit and both of them > > are inverting. This removes the effects of common mode changes. The > > gain control is done either with a light controlled resistor or a > > couple of thermistors. It takes quite a while for the amplitude to > > settle but the noise and distortion values come out very good. > > I have a HP 8903B, which is a decent source. I'm not sure you could > roll something together that is better. > > I remember building the Wein bridge oscillator in school. We used a > jfet for the gain control.
The JFET leads to a lot of even order harmonics. HP used a light bulb in their early designs. Some people have used things like car head lamps to get massive enough devices. The Wein bridge design is not very accurate as far as frequency but it can be very low noise and distortion.
Andrew Holme wrote:

> > "Paul Russell" <prussell@sonic.net> wrote in message > news:5anvbhF2om6lkU1@mid.individual.net... >> Andrew Holme wrote: >>> "Andrew Holme" <andrew@nospam.com> wrote in message >>> news:f25gke$dlo$1$8302bc10@news.demon.co.uk... >>>> I computed this forward FFT using MS VC++ 6.0 and FFTW: >>>> >>>> http://www.holmea.demon.co.uk/Misc/FFT.gif >>>> >>>> I don't think the "tail" should flick up like that at the low-frequency >>>> end. Is this caused by a lack of floating-point precision? >>> >>> My C++ program generates 1e6 samples of aperiodic data, sampled at Ts = >>> 1 MHz i.e. duration = 1 second; and I want to analyse the frequency >>> content. I'm using an FFT; but I'm getting a strong response in the FFT >>> output at 1 Hz. This would be correct if the same 1e6 samples repeated, >>> but they don't. Is there any way to reduce this effect, or is it a >>> fundamental limitation of the FFT? >> >> This is probably just spectral leakage from the DC bin - my guess is that >> you are not applying an appropriate windowing function to the data prior >> to the FFT ? >> >> Paul > > Eliminating the DC component did not help. I am not using a windowing > function at the moment. Can you suggest one? I don't mind sacrificing > frequency resolution.
I did not expect it to, but held my peace. The tail is in part created by two things, the end around discontinuity, and the fact that your sampling frequency is insufficient to get a worthwhile spectrum of the switcher. Please note that the expected (mostly odd) harmonics are missing. Try about 10 (or 100) times the sample rate for about one 50th as long a time. Then do the DFT twice and plot 50 us (5 cycles of the switcher) and see what you get. I promise that the 10 MHz sample rate will produce a much more believable waveform. -- JosephKK Gegen dummheit kampfen die Gotter Selbst, vergebens.&nbsp;&nbsp; --Schiller