Hi, I am searching a way to implement FIR with more taps through efficient way, for example, implement 48 taps FIR for WCDMA with as little as possible multipliers and adders. I searched the web and could find two solutions: one way is to do something like what textbook states, use 48 multipliers and more adders; the other way is to implement it use pipeline structure with increased frequency. The structure of pipeline reduces resource dramatically, but it works with high frequency. This may be a challenge in the design. Is there any other suggestion for the design? or does anybody knows how other engineer implement this kind of filter in their design? thanks very much.
FIR design
Started by ●May 31, 2007
Reply by ●May 31, 20072007-05-31
skyworld wrote:> Hi, > > I am searching a way to implement FIR with more taps through efficient > way, for example, implement 48 taps FIR for WCDMA with as little as > possible multipliers and adders. I searched the web and could find two > solutions: one way is to do something like what textbook states, use > 48 multipliers and more adders; the other way is to implement it use > pipeline structure with increased frequency. The structure of pipeline > reduces resource dramatically, but it works with high frequency. This > may be a challenge in the design. Is there any other suggestion for > the design? or does anybody knows how other engineer implement this > kind of filter in their design? thanks very much.Is your filter symmetric (or antisymmetric)? If so, you can replace half the multipliers with adders (or subtracters). Jerry -- Engineering is the art of making what you want from things you can get. ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
Reply by ●May 31, 20072007-05-31
On May 31, 8:14 am, Jerry Avins <j...@ieee.org> wrote:> Is your filter symmetric (or antisymmetric)? If so, you can replace half > the multipliers with adders (or subtracters). > > JerryOr, use something like the Canonical Signed Digits (CSD) structure.... Julius
Reply by ●May 31, 20072007-05-31
julius <juliusk@gmail.com> writes:> On May 31, 8:14 am, Jerry Avins <j...@ieee.org> wrote: >> Is your filter symmetric (or antisymmetric)? If so, you can replace half >> the multipliers with adders (or subtracters). >> >> Jerry > > Or, use something like the Canonical Signed Digits (CSD) structure....Or, if it's a lowpass type, a half-band filter may be useful, in which case half of the coefficients are zero. See [lyonsnew]. --Randy @BOOK{lyonsnew, title = "{Understanding Digital Signal Processing}", edition = "Second", author = "{Richard~G.~Lyons}", publisher = "Prentice Hall", year = "2004"} -- % Randy Yates % "How's life on earth? %% Fuquay-Varina, NC % ... What is it worth?" %%% 919-577-9882 % 'Mission (A World Record)', %%%% <yates@ieee.org> % *A New World Record*, ELO http://home.earthlink.net/~yatescr
Reply by ●May 31, 20072007-05-31
Randy Yates <yates@ieee.org> writes:> julius <juliusk@gmail.com> writes: > >> On May 31, 8:14 am, Jerry Avins <j...@ieee.org> wrote: >>> Is your filter symmetric (or antisymmetric)? If so, you can replace half >>> the multipliers with adders (or subtracters). >>> >>> Jerry >> >> Or, use something like the Canonical Signed Digits (CSD) structure.... > > Or, if it's a lowpass type, a half-band filter may be useful, in which > case half of the coefficients are zero. See [lyonsnew].And if you don't need the full sample rate at the filter output, you could also decimate, in which case you use polyphase filtering to save operations. Let's take an example incorporating three of these: say you have a symmetric (or antisymmetric) half-band filter with 48 taps and you're decimating by two. Then you can get away with 48 / 2 (for symmetry) / 2 (for half-band) / 2 (for polyphase decimation) = 6 multiplies per output Neat, huh? -- % Randy Yates % "I met someone who looks alot like you, %% Fuquay-Varina, NC % she does the things you do, %%% 919-577-9882 % but she is an IBM." %%%% <yates@ieee.org> % 'Yours Truly, 2095', *Time*, ELO http://home.earthlink.net/~yatescr
Reply by ●May 31, 20072007-05-31
"Randy Yates" <yates@ieee.org> wrote in message news:m3tzttp0ck.fsf@ieee.org...> Randy Yates <yates@ieee.org> writes: > >> julius <juliusk@gmail.com> writes: >> >>> On May 31, 8:14 am, Jerry Avins <j...@ieee.org> wrote: >>>> Is your filter symmetric (or antisymmetric)? If so, you can replace >>>> half >>>> the multipliers with adders (or subtracters). >>>> >>>> Jerry >>> >>> Or, use something like the Canonical Signed Digits (CSD) structure.... >> >> Or, if it's a lowpass type, a half-band filter may be useful, in which >> case half of the coefficients are zero. See [lyonsnew]. > > And if you don't need the full sample rate at the filter output, you > could also decimate, in which case you use polyphase filtering to > save operations. > > Let's take an example incorporating three of these: say you have a > symmetric (or antisymmetric) half-band filter with 48 taps and > you're decimating by two. Then you can get away with > > 48 / 2 (for symmetry) / 2 (for half-band) / 2 (for polyphase decimation) > = 6 multiplies per output > > Neat, huh?One time-honored approach is to truncate the coefficients to "sums of powers of two" and to do all or most of the filter implementation with shifts and adds. A lot depends on the hardware and what drives the "cost function" - i.e. it may be money or real estate or .... There are enough threads on comp.dsp that discuss this that a good search should get you all those discussions on methods, etc. Fred
Reply by ●May 31, 20072007-05-31
On May 31, 1:34 am, skyworld <chenyong20...@gmail.com> wrote:> Hi, > > I am searching a way to implement FIR with more taps through efficient > way, for example, implement 48 taps FIR for WCDMA with as little as > possible multipliers and adders. I searched the web and could find two > solutions: one way is to do something like what textbook states, use > 48 multipliers and more adders; the other way is to implement it use > pipeline structure with increased frequency. The structure of pipeline > reduces resource dramatically, but it works with high frequency. This > may be a challenge in the design. Is there any other suggestion for > the design? or does anybody knows how other engineer implement this > kind of filter in their design? thanks very much.Hi, It sounds like you want to implement this FIR filter in hardware (either FPGA or ASIC), since you mentioned WCDMA with it's high data rates. If so, there's a new EDA tool which creates FIR filters in clear text Verilog HDL (so you can easily port your design if you change FPGA or ASIC vendors). Supported features include multiple channels, multiple coefficient sets, interpolation and decimation. It even makes a Verilog testbench for impulse, step and random response. Information is available at : http://www.optunis.com/fir_hdl_writer/fir_hdl_writer_info.html Best Regards, Tony
Reply by ●May 31, 20072007-05-31
On Thu, 31 May 2007 14:47:30 -0700, "Fred Marshall" <fmarshallx@remove_the_x.acm.org> wrote:> >"Randy Yates" <yates@ieee.org> wrote in message >news:m3tzttp0ck.fsf@ieee.org... >> Randy Yates <yates@ieee.org> writes: >> >>> julius <juliusk@gmail.com> writes: >>> >>>> On May 31, 8:14 am, Jerry Avins <j...@ieee.org> wrote: >>>>> Is your filter symmetric (or antisymmetric)? If so, you can replace >>>>> half >>>>> the multipliers with adders (or subtracters). >>>>> >>>>> Jerry >>>> >>>> Or, use something like the Canonical Signed Digits (CSD) structure.... >>> >>> Or, if it's a lowpass type, a half-band filter may be useful, in which >>> case half of the coefficients are zero. See [lyonsnew]. >> >> And if you don't need the full sample rate at the filter output, you >> could also decimate, in which case you use polyphase filtering to >> save operations. >> >> Let's take an example incorporating three of these: say you have a >> symmetric (or antisymmetric) half-band filter with 48 taps and >> you're decimating by two. Then you can get away with >> >> 48 / 2 (for symmetry) / 2 (for half-band) / 2 (for polyphase decimation) >> = 6 multiplies per output >> >> Neat, huh? > >One time-honored approach is to truncate the coefficients to "sums of powers >of two" and to do all or most of the filter implementation with shifts and >adds. A lot depends on the hardware and what drives the "cost function" - >i.e. it may be money or real estate or ....That's the simpler description of the more fancy-named CSD, Canonic Signed Digits, approach that Julius suggested.>There are enough threads on comp.dsp that discuss this that a good search >should get you all those discussions on methods, etc. > >FredIf the filter in question isn't the pulse-shaping filter, then other efficient approaches like CIC, Cascaded Integrator-Comb or just cascaded FIR filters...like you say, there are lots of threads on this stuff. Eric Jacobsen Minister of Algorithms Abineau Communications http://www.ericjacobsen.org
Reply by ●June 1, 20072007-06-01
On 5=D4=C231=C8=D5, =CF=C2=CE=E79=CA=B128=B7=D6, julius <juli...@gmail.com>= wrote:> On May 31, 8:14 am, Jerry Avins <j...@ieee.org> wrote: > > > Is your filter symmetric (or antisymmetric)? If so, you can replace half > > the multipliers with adders (or subtracters). > > > Jerry > > Or, use something like the Canonical Signed Digits (CSD) structure.... > > JuliusHi Julius, can you explain what is CSD structure? thanks very mcuh. skyworld
Reply by ●June 1, 20072007-06-01
On 5=D4=C231=C8=D5, =CF=C2=CE=E79=CA=B151=B7=D6, Randy Yates <y...@ieee.org=> wrote: > Randy Yates <y...@ieee.org> writes: > > julius <juli...@gmail.com> writes: > > >> On May 31, 8:14 am, Jerry Avins <j...@ieee.org> wrote: > >>> Is your filter symmetric (or antisymmetric)? If so, you can replace h=alf> >>> the multipliers with adders (or subtracters). > > >>> Jerry > > >> Or, use something like the Canonical Signed Digits (CSD) structure.... > > > Or, if it's a lowpass type, a half-band filter may be useful, in which > > case half of the coefficients are zero. See [lyonsnew]. > > And if you don't need the full sample rate at the filter output, you > could also decimate, in which case you use polyphase filtering to > save operations. > > Let's take an example incorporating three of these: say you have a > symmetric (or antisymmetric) half-band filter with 48 taps and > you're decimating by two. Then you can get away with > > 48 / 2 (for symmetry) / 2 (for half-band) / 2 (for polyphase decimation) > =3D 6 multiplies per output > > Neat, huh? > -- > % Randy Yates % "I met someone who looks alot like you, > %% Fuquay-Varina, NC % she does the things you do, > %%% 919-577-9882 % but she is an IBM." > %%%% <y...@ieee.org> % 'Yours Truly, 2095', *Time*, ELO =http://home.earthlink.net/~yatescr well, I think the filter is not a half-band one. skyworld
