In the maunal of TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide(spru732d.pdf) On the page 31, there is a sentence, "Fully pipelined branches: zero- overhead branching". But on the page 610, it mentions brach instructions "Although branch instructions take one execute phase, there are five delay slots between the execution of the branch and execution of the target code." In my opinion,five delay slots is overhead.What does zero-overhead mean? Thanks in advance. Jogging
zero-overhead branching
Started by ●August 18, 2007
Reply by ●August 18, 20072007-08-18
joggingsong@gmail.com wrote:> In the maunal of TMS320C64x/C64x+ DSP CPU and Instruction Set > Reference Guide(spru732d.pdf) > On the page 31, there is a sentence, "Fully pipelined branches: zero- > overhead branching". > But on the page 610, it mentions brach instructions > "Although branch instructions take one execute phase, there are five > delay > slots between the execution of the branch and execution of the target > code." > > In my opinion,five delay slots is overhead.What does zero-overhead > mean? > Thanks in advance.Useful instructions can be executed in those delay slots. Pipeline adds new considerations to low-level programming. Jerry -- Engineering is the art of making what you want from things you can get. ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
Reply by ●August 18, 20072007-08-18
On Sat, 18 Aug 2007 07:36:23 +0000, joggingsong wrote:> In the maunal of TMS320C64x/C64x+ DSP CPU and Instruction Set > Reference Guide(spru732d.pdf) > On the page 31, there is a sentence, "Fully pipelined branches: zero- > overhead branching". > But on the page 610, it mentions brach instructions > "Although branch instructions take one execute phase, there are five > delay > slots between the execution of the branch and execution of the target > code." > > In my opinion,five delay slots is overhead.What does zero-overhead > mean? > Thanks in advance. > > JoggingYou confuse "overhead" with "delay". In a pipelined processor, _everything_ is delayed by the pipeline latency, but that doesn't mean you can't get one instruction out of the pipeline for each clock tick. -- Tim Wescott Control systems and communications consulting http://www.wescottdesign.com Need to learn how to apply control theory in your embedded system? "Applied Control Theory for Embedded Systems" by Tim Wescott Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html
Reply by ●August 18, 20072007-08-18
On Aug 18, 9:23 am, Tim Wescott <t...@seemywebsite.com> wrote:> On Sat, 18 Aug 2007 07:36:23 +0000, joggingsong wrote: > > In the maunal of TMS320C64x/C64x+ DSP CPU and Instruction Set > > Reference Guide(spru732d.pdf) > > On the page 31, there is a sentence, "Fully pipelined branches: zero- > > overhead branching". > > But on the page 610, it mentions brach instructions > > "Although branch instructions take one execute phase, there are five > > delay > > slots between the execution of the branch and execution of the target > > code." > > > In my opinion,five delay slots is overhead.What does zero-overhead > > mean? > > Thanks in advance. > > > Jogging > > You confuse "overhead" with "delay". In a pipelined processor, > _everything_ is delayed by the pipeline latency, but that doesn't mean > you can't get one instruction out of the pipeline for each clock tick. > > -- > Tim Wescott > Control systems and communications consultinghttp://www.wescottdesign.com > > Need to learn how to apply control theory in your embedded system? > "Applied Control Theory for Embedded Systems" by Tim Wescott > Elsevier/Newnes,http://www.wescottdesign.com/actfes/actfes.htmlI believe a TI C33 executes 3 instructions after the branch delayed instruction. If you don't have three instructions to put there you better have NOP instructions there instead. Since the TI compiler does a miserable job of making use of delay branches I must write tight code in assembly language. Peter Nachtwey
Reply by ●August 18, 20072007-08-18
pnachtwey@gmail.com wrote: ...> I believe a TI C33 executes 3 instructions after the branch delayed > instruction. If you don't have three instructions to put there you > better have NOP instructions there instead. Since the TI compiler > does a miserable job of making use of delay branches I must write > tight code in assembly language.Amen to that! jerry -- Engineering is the art of making what you want from things you can get. ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
Reply by ●August 20, 20072007-08-20
On Aug 18, 10:17 pm, Jerry Avins <j...@ieee.org> wrote:> joggings...@gmail.com wrote: > > In the maunal of TMS320C64x/C64x+ DSP CPU and Instruction Set > > Reference Guide(spru732d.pdf) > > On the page 31, there is a sentence, "Fully pipelined branches: zero- > > overhead branching". > > But on the page 610, it mentions brach instructions > > "Although branch instructions take one execute phase, there are five > > delay > > slots between the execution of the branch and execution of the target > > code." > > > In my opinion,five delay slots is overhead.What does zero-overhead > > mean? > > Thanks in advance. > > Useful instructions can be executed in those delay slots. Pipeline adds > new considerations to low-level programming. > > Jerry > -- > Engineering is the art of making what you want from things you can get. > =AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF==AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF= =AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF How can it make it? It is done by c compiler? Jogging
Reply by ●August 20, 20072007-08-20
joggingsong@gmail.com wrote:> On Aug 18, 10:17 pm, Jerry Avins <j...@ieee.org> wrote:...>> Useful instructions can be executed in those delay slots. Pipeline adds >> new considerations to low-level programming....> How can it make it? It is done by c compiler?I'm sure that the manual gives some examples of efficient use of the pipeline. I don't know how successfully your compiler does it, but most make an attempt to use the delay slots efficiently. jerry -- Engineering is the art of making what you want from things you can get. ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
Reply by ●August 20, 20072007-08-20
pnachtwey@gmail.com wrote:> On Aug 18, 9:23 am, Tim Wescott <t...@seemywebsite.com> wrote: >> On Sat, 18 Aug 2007 07:36:23 +0000, joggingsong wrote: >>> In the maunal of TMS320C64x/C64x+ DSP CPU and Instruction Set >>> Reference Guide(spru732d.pdf) >>> On the page 31, there is a sentence, "Fully pipelined branches: zero- >>> overhead branching". >>> But on the page 610, it mentions brach instructions >>> "Although branch instructions take one execute phase, there are five >>> delay >>> slots between the execution of the branch and execution of the target >>> code." >>> In my opinion,five delay slots is overhead.What does zero-overhead >>> mean? >>> Thanks in advance. >>> Jogging >> You confuse "overhead" with "delay". In a pipelined processor, >> _everything_ is delayed by the pipeline latency, but that doesn't mean >> you can't get one instruction out of the pipeline for each clock tick. >> >> -- >> Tim Wescott >> Control systems and communications consultinghttp://www.wescottdesign.com >> >> Need to learn how to apply control theory in your embedded system? >> "Applied Control Theory for Embedded Systems" by Tim Wescott >> Elsevier/Newnes,http://www.wescottdesign.com/actfes/actfes.html > > I believe a TI C33 executes 3 instructions after the branch delayed > instruction. If you don't have three instructions to put there you > better have NOP instructions there instead. Since the TI compiler > does a miserable job of making use of delay branches I must write > tight code in assembly language. >Whenever I approach a DSP coding project I always try to identify the 1% of the code that will get called 99% of the time. That part gets coded in assembly by hand (and usually by my hand). The rest gets done in C or C++ (and largely by minions when I have them). -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" gives you just what it says. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●August 20, 20072007-08-20
Tim Wescott wrote:> Whenever I approach a DSP coding project I always try to identify the 1% > of the code that will get called 99% of the time. That part gets coded > in assembly by hand (and usually by my hand). The rest gets done in C > or C++ (and largely by minions when I have them).It looks surprising but the asm coding of the narrow places can be done by apprentices fairly well. This is because the asm part is usually quite small, straightforward and very clearly defined. Unfortunately, the hardware interface layer and the general frame of the application has to be coded by master... This is what they just can't understand. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●August 20, 20072007-08-20
Vladimir Vassilevsky wrote:> > > Tim Wescott wrote: > >> Whenever I approach a DSP coding project I always try to identify the >> 1% of the code that will get called 99% of the time. That part gets >> coded in assembly by hand (and usually by my hand). The rest gets >> done in C or C++ (and largely by minions when I have them). > > It looks surprising but the asm coding of the narrow places can be done > by apprentices fairly well. This is because the asm part is usually > quite small, straightforward and very clearly defined.Yes, and the ability of a novice who understands the processor architecture to do it well, coupled with the received wisdom that asm programming is universally hard, can give said novice a false sense of guruhood.> Unfortunately, the hardware interface layer and the general frame of the > application has to be coded by master... This is what they just can't > understand.Who is "they"? In my experience, the master has to design the approach. The actual coding is then often simple enough for an apprentice, but it's probably easier for Master to do it than to describe what needs doing. I often spent more time guiding my technicians than the job would have taken me, but it was time well spent. Good help is hard to find; you have to make it. (Two of my techs became MTSs.) Jerry -- Engineering is the art of making what you want from things you can get. ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
