CIC filter payoff

Started by kungcoccos November 12, 2007
Hello everyone!

Im in the middle of my thesis and one of the objects that the company want
to know is:

When will a implementation of a CIC filter payoff? After some time
spending with such as Hougenauger's and Donadio's publications, I still
can't find out when the CIC really gets economical.

So to be concrete, the questions are:

When does the CIC filter gets economical in terms of
interpolation/decimation factor?

Which is the highest passband I can use at a CIC?

Its pretty clear for me that its tradeoffs between all these things. Maybe
you guys can help me with som "rule of thumbs", or even better, som
sources?

Thank you!=)



On Nov 12, 4:08 pm, "kungcoccos" <c...@hallqvist.biz> wrote:
> Hello everyone! > > Im in the middle of my thesis and one of the objects that the company want > to know is: > > When will a implementation of a CIC filter payoff? After some time > spending with such as Hougenauger's and Donadio's publications, I still > can't find out when the CIC really gets economical. > > So to be concrete, the questions are: > > When does the CIC filter gets economical in terms of > interpolation/decimation factor? > > Which is the highest passband I can use at a CIC? > > Its pretty clear for me that its tradeoffs between all these things. Maybe > you guys can help me with som "rule of thumbs", or even better, som > sources?
It's a difficult question to come up with "rules of thumb" for. It depends entirely on how good you want your alias-rejection to be, how much in-band droop you can tolerate, and how "expensive" multiplies are on your target hardware. On a low-power, low-cost, low-size ASIC, for instance, multiply units are definitely expensive. On a DSP, there's probably no advantage to the CIC approach at all. (However, the overall filter responses can still be pretty nifty.) As for passband width, generally speaking, once it's above 10% to 20% of Nyquist, the compensation filter you need to prevent in-band rolloff starts becoming more and more aggressive, and therefore more and more computationally heavy. Plus, the compensation filter will artificially increase the noise at the passband edges. -- Oli
kungcoccos wrote:

> Hello everyone! > > Im in the middle of my thesis and one of the objects that the company want > to know is: > > When will a implementation of a CIC filter payoff? After some time > spending with such as Hougenauger's and Donadio's publications, I still > can't find out when the CIC really gets economical. > > So to be concrete, the questions are: > > When does the CIC filter gets economical in terms of > interpolation/decimation factor?
It depends on your target technology, filter bank requirements etc. The CIC is nearly essential if you have bandwidth that can be set to different widths, because it can be changed by changing only the CIC's decimation ratio and without touching any of the other filters in the system. That is because the CIC's filter response referred to the decimated output sample rate is virtually independent of the decimation ratio (there is a small dependence on decimation ratio which is most noticible at very low decimation ratios, but even there is very small).
> > Which is the highest passband I can use at a CIC?
The usable passband depends on how much droop you can accept and/or correct. I typically use FIR filters after the CIC to further decimate by 4 in order to restrict the passband to something less than 1/4 of the first null in the CIC response. With that, you can follow the FIR filters with a small (~5 taps) filter to compensate for the CIC roll-off within the passband, which might be a few dB.
> > Its pretty clear for me that its tradeoffs between all these things. Maybe > you guys can help me with som "rule of thumbs", or even better, som > sources? > > Thank you!=) > > >
>On Nov 12, 4:08 pm, "kungcoccos" <c...@hallqvist.biz> wrote: >> Hello everyone! >> >> Im in the middle of my thesis and one of the objects that the company
want
>> to know is: >> >> When will a implementation of a CIC filter payoff? After some time >> spending with such as Hougenauger's and Donadio's publications, I
still
>> can't find out when the CIC really gets economical. >> >> So to be concrete, the questions are: >> >> When does the CIC filter gets economical in terms of >> interpolation/decimation factor? >> >> Which is the highest passband I can use at a CIC? >> >> Its pretty clear for me that its tradeoffs between all these things.
Maybe
>> you guys can help me with som "rule of thumbs", or even better, som >> sources? > >It's a difficult question to come up with "rules of thumb" for. It >depends entirely on how good you want your alias-rejection to be, how >much in-band droop you can tolerate, and how "expensive" multiplies >are on your target hardware. On a low-power, low-cost, low-size ASIC, >for instance, multiply units are definitely expensive. On a DSP, >there's probably no advantage to the CIC approach at all. (However, >the overall filter responses can still be pretty nifty.) > >As for passband width, generally speaking, once it's above 10% to 20% >of Nyquist, the compensation filter you need to prevent in-band >rolloff starts becoming more and more aggressive, and therefore more >and more computationally heavy. Plus, the compensation filter will >artificially increase the noise at the passband edges. > > >-- >Oli > >
Thanks for your advices. Is it anything written in this subject or is it "well-known" at DSP-people? As I told you, I havent seen anything about it. Furthermore, can you give me some practical examples where the CIC is a optimal or at least, good solution in FPGA architechtures? Finally, can you recommend some others designs that are used as interpolation/decimation filters?
On Nov 12, 7:40 pm, "kungcoccos" <c...@hallqvist.biz> wrote:
> >On Nov 12, 4:08 pm, "kungcoccos" <c...@hallqvist.biz> wrote: > >> Hello everyone! > > >> Im in the middle of my thesis and one of the objects that the company > want > >> to know is: > > >> When will a implementation of a CIC filter payoff? After some time > >> spending with such as Hougenauger's and Donadio's publications, I > still > >> can't find out when the CIC really gets economical. > > >> So to be concrete, the questions are: > > >> When does the CIC filter gets economical in terms of > >> interpolation/decimation factor? > > >> Which is the highest passband I can use at a CIC? > > >> Its pretty clear for me that its tradeoffs between all these things. > Maybe > >> you guys can help me with som "rule of thumbs", or even better, som > >> sources? > > >It's a difficult question to come up with "rules of thumb" for. It > >depends entirely on how good you want your alias-rejection to be, how > >much in-band droop you can tolerate, and how "expensive" multiplies > >are on your target hardware. On a low-power, low-cost, low-size ASIC, > >for instance, multiply units are definitely expensive. On a DSP, > >there's probably no advantage to the CIC approach at all. (However, > >the overall filter responses can still be pretty nifty.) > > >As for passband width, generally speaking, once it's above 10% to 20% > >of Nyquist, the compensation filter you need to prevent in-band > >rolloff starts becoming more and more aggressive, and therefore more > >and more computationally heavy. Plus, the compensation filter will > >artificially increase the noise at the passband edges. > > Thanks for your advices. Is it anything written in this subject or > is it "well-known" at DSP-people? As I told you, I havent seen anything > about it.
This is a good article, and where I got started on CICs. It's by Rick Lyons, who also happens to frequent this newsgroup. http://www.us.design-reuse.com/articles/10028/understanding-cascaded-integrator-comb-filters.html
> Furthermore, can you give me some practical examples where the CIC is a > optimal or at least, good solution in FPGA architechtures?
It depends what you mean by "optimal". Certainly, given certain design constraints and assumptions, then a CIC may give the lowest gate count, as very few multiplies are required. However, if your optimality criterion is "how close can I get to a given filter response?", then the only way to do that is to use a "normal" filter architecture, designed with, e.g. the Parks-McLellan algorithm.
> Finally, can you recommend some others designs that are used as > interpolation/decimation filters?
I'm not an expert on FPGA design, I'm afraid. However, the "standard" DSP approach is to use a polyphase filter (which take advantage of the fact that many of the input samples will be zero, or that many of the output values are thrown away). Typically, if your resampling ratio is high, then the downsampling is done in several stages (e.g. down- by-30 might be achieved with a down-by-2, followed by a down-by-3 and then a down-by-5). In some special cases, you may be able to use a "half-band" filter, which has the advantage that half of the coefficients are zero. The Farrow architecture is also fairly common; this has the advantage that it allows arbitrary-ratio resampling, and is based on polynomial interpolation. -- Oli
>On Nov 12, 7:40 pm, "kungcoccos" <c...@hallqvist.biz> wrote: >> >On Nov 12, 4:08 pm, "kungcoccos" <c...@hallqvist.biz> wrote: >> >> Hello everyone! >> >> >> Im in the middle of my thesis and one of the objects that the
company
>> want >> >> to know is: >> >> >> When will a implementation of a CIC filter payoff? After some time >> >> spending with such as Hougenauger's and Donadio's publications, I >> still >> >> can't find out when the CIC really gets economical. >> >> >> So to be concrete, the questions are: >> >> >> When does the CIC filter gets economical in terms of >> >> interpolation/decimation factor? >> >> >> Which is the highest passband I can use at a CIC? >> >> >> Its pretty clear for me that its tradeoffs between all these
things.
>> Maybe >> >> you guys can help me with som "rule of thumbs", or even better, som >> >> sources? >> >> >It's a difficult question to come up with "rules of thumb" for. It >> >depends entirely on how good you want your alias-rejection to be, how >> >much in-band droop you can tolerate, and how "expensive" multiplies >> >are on your target hardware. On a low-power, low-cost, low-size
ASIC,
>> >for instance, multiply units are definitely expensive. On a DSP, >> >there's probably no advantage to the CIC approach at all. (However, >> >the overall filter responses can still be pretty nifty.) >> >> >As for passband width, generally speaking, once it's above 10% to 20% >> >of Nyquist, the compensation filter you need to prevent in-band >> >rolloff starts becoming more and more aggressive, and therefore more >> >and more computationally heavy. Plus, the compensation filter will >> >artificially increase the noise at the passband edges. >> >> Thanks for your advices. Is it anything written in this subject or >> is it "well-known" at DSP-people? As I told you, I havent seen
anything
>> about it. > >This is a good article, and where I got started on CICs. It's by Rick >Lyons, who also happens to frequent this newsgroup. >http://www.us.design-reuse.com/articles/10028/understanding-cascaded-integrator-comb-filters.html > > >> Furthermore, can you give me some practical examples where the CIC is
a
>> optimal or at least, good solution in FPGA architechtures? > >It depends what you mean by "optimal". Certainly, given certain >design constraints and assumptions, then a CIC may give the lowest >gate count, as very few multiplies are required. However, if your >optimality criterion is "how close can I get to a given filter >response?", then the only way to do that is to use a "normal" filter >architecture, designed with, e.g. the Parks-McLellan algorithm. > > >> Finally, can you recommend some others designs that are used as >> interpolation/decimation filters? > >I'm not an expert on FPGA design, I'm afraid. However, the "standard" >DSP approach is to use a polyphase filter (which take advantage of the >fact that many of the input samples will be zero, or that many of the >output values are thrown away). Typically, if your resampling ratio >is high, then the downsampling is done in several stages (e.g. down- >by-30 might be achieved with a down-by-2, followed by a down-by-3 and >then a down-by-5). In some special cases, you may be able to use a >"half-band" filter, which has the advantage that half of the >coefficients are zero. > >The Farrow architecture is also fairly common; this has the advantage >that it allows arbitrary-ratio resampling, and is based on polynomial >interpolation. > >-- >Oli > >
Thanks a lot, it was that kind of information I was looking for. =)
kungcoccos wrote:
>> On Nov 12, 4:08 pm, "kungcoccos" <c...@hallqvist.biz> wrote: >>> Hello everyone! >>> >>> Im in the middle of my thesis and one of the objects that the company > want >>> to know is: >>> >>> When will a implementation of a CIC filter payoff? After some time >>> spending with such as Hougenauger's and Donadio's publications, I > still >>> can't find out when the CIC really gets economical. >>> >>> So to be concrete, the questions are: >>> >>> When does the CIC filter gets economical in terms of >>> interpolation/decimation factor? >>> >>> Which is the highest passband I can use at a CIC? >>> >>> Its pretty clear for me that its tradeoffs between all these things. > Maybe >>> you guys can help me with som "rule of thumbs", or even better, som >>> sources? >> It's a difficult question to come up with "rules of thumb" for. It >> depends entirely on how good you want your alias-rejection to be, how >> much in-band droop you can tolerate, and how "expensive" multiplies >> are on your target hardware. On a low-power, low-cost, low-size ASIC, >> for instance, multiply units are definitely expensive. On a DSP, >> there's probably no advantage to the CIC approach at all. (However, >> the overall filter responses can still be pretty nifty.) >> >> As for passband width, generally speaking, once it's above 10% to 20% >> of Nyquist, the compensation filter you need to prevent in-band >> rolloff starts becoming more and more aggressive, and therefore more >> and more computationally heavy. Plus, the compensation filter will >> artificially increase the noise at the passband edges. >> >> >> -- >> Oli >> >> > Thanks for your advices. Is it anything written in this subject or > is it "well-known" at DSP-people? As I told you, I havent seen anything > about it. > > Furthermore, can you give me some practical examples where the CIC is a > optimal or at least, good solution in FPGA architechtures? > > Finally, can you recommend some others designs that are used as > interpolation/decimation filters? >
CIC filters give their best advantage where multiplications are really expensive. In an FPGA, this happens when you're using the multiplier blocks somewhere else, or if you're using a really small multiplier block. It happens pretty much instantly in an ASIC, because fast multipliers are space and power hogs, so you'd like to get away from them entirely. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" gives you just what it says. See details at http://www.wescottdesign.com/actfes/actfes.html
kungcoccos wrote:
>>On Nov 12, 4:08 pm, "kungcoccos" <c...@hallqvist.biz> wrote:
> > Thanks for your advices. Is it anything written in this subject or > is it "well-known" at DSP-people? As I told you, I havent seen anything > about it.
There is bits and pieces in various publications. Freking's DSP in communications systems text has a pretty good write-up on CIC filters, and is more practical/readable than Hogenaur's paper. My knowledge of the CIC comes mostly from using it in literally dozens of designs, including a few that were kind of off-the-wall.
> > Furthermore, can you give me some practical examples where the CIC is a > optimal or at least, good solution in FPGA architechtures?
1) High decimation or interpolation ratios, as found in a narrow band receiver with a wide tuning range. The input sample rate is quite high to accommodate the tuning range, but the bandwidth of the signal is narrow. The CIC is the most efficient way to do high order decimations (for example decimate by 1600). Gray chip uses a CIC in some of their digital reciever ASSPs as well. 2) Applications where the same hardware has to deal with different decimation ratios but provide the same shape factor of the signal regardless of the sample rate. For example a digital receiver that is used for recieving telemetry signals from different sources at different datqa rates. The CIC provides a mechanism for easily changing the bandwidth and decimated sample rate without changing the ratio of the bandwidth to the output sample rate. I've done several such recievers. The advantage here is the clean-up filters that follow the CIC do not have to change at all when the bandwidth/sampling rate gets changed because the CIC response referred to the output sample rate is virtually independent of the decimation ratio. Works for interpolation in the transmitter as well. The CIC nearly always needs to be followed by a pass band shaping filter to get the desired response, and that filter or filter bank is usually a decimate by 4 or more to get the passband well inside the CIC so that a) the passband rolloff is not excessive, and b) the passband falls into the nulls without too much climbing the sides of the nulls, which would require a higher order CIC. The CIC takes the place of a series of half-band decimators in a polyphase filter. It become economical for a fixed decimation ratio when the adders in the CIC take up less logic than the cascade of half-band decimators would take to get an equivalent decimation. Typically, break even occurs by the time the CIC decimation ratio reaches 4, but it really depends on the filter requirements, including passband flatness, stop band attenuation etc.
> > Finally, can you recommend some others designs that are used as > interpolation/decimation filters?
Polyphase decimators banks use multi-rate filtering with the earlier stages typically half-band decimate by 2 stages. Each time the sample rate is dropped, you get more processing per unit time for a given amount of hardware. A series of decimate by 2 stages is the most efficient computation wise for multi-rate filters, but can be challenging for noise. beyond a couple of stages, you'll want to use a CIC followed by a few decimating FIR filters.
>