Second order delta-sigma modulator. How?

Hi,
I tried to get an answer to this when it came up on comp.arch.fpga but
didn't get anywhere. So, Mr Bromley posted as quoted below about algorithms
for first order delta-sigma modulators. My question is:-
What's the algorithm for a second order delta-sigma modulator? N-order? I
tried Googling but struggled to find a clear answer. The Maxim site had some
app. notes about their converters, but this still didn't help me. Any
pointers gratefully received. TIA.
Cheers, Syms.

"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message
news:kc9780d765fn0lor7msd06dhnk033aqp7p@4ax.com...
> You can make a simple
> distributed PWM by using a first order delta-sigma modulator;
> it's essentially the same trick as Bresenham's algorithm
> for drawing angled lines on a raster display.  Conceptually
> the algorithm is:
>   * maintain a signed accumulator register A
>   * establish a PWM cycle length, N clock cycles
>   * have a "desired output" value V
>   * on each clock cycle, accumulate A = A + V, and then...
>     - if A is negative, supply 0 as the output
>     - if A is positive, supply 1 as the output and modify
>       the accumulator by forming A = A - N
>

Hey Symon,

An Lth-order modulator yields a noise transfer function of H(z) =
(1-z^(-1))^L. The power response of this is |H(\omega)|^2 = [2*(1 -
cos(\omega))]^L.

Note this is for a cascade of simple integrators in the modulator
loop. More sophisticated transfer functions can be constructed.

I recommend the following reference: 

@BOOK{deltasigmadataconverters,
  title = "Delta-Sigma Data Converters: Theory, Design, and Simulation",
  author = "{Steven~R.~Norsworthy,} {Richard~Schreier,} and {Gabor~C.~Temes}",
  publisher = "IEEE Press",
  year = "1997"}

Also note that there is a survey of delta sigma techniques in the current issue
of the Journal of the Audio Engineering Society.

--Randy

"Symon" <symon_brewer@hotmail.com> writes:

> Hi,
> I tried to get an answer to this when it came up on comp.arch.fpga but
> didn't get anywhere. So, Mr Bromley posted as quoted below about algorithms
> for first order delta-sigma modulators. My question is:-
> What's the algorithm for a second order delta-sigma modulator? N-order? I
> tried Googling but struggled to find a clear answer. The Maxim site had some
> app. notes about their converters, but this still didn't help me. Any
> pointers gratefully received. TIA.
> Cheers, Syms.
>
> "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message
> news:kc9780d765fn0lor7msd06dhnk033aqp7p@4ax.com...
>> You can make a simple
>> distributed PWM by using a first order delta-sigma modulator;
>> it's essentially the same trick as Bresenham's algorithm
>> for drawing angled lines on a raster display.  Conceptually
>> the algorithm is:
>>   * maintain a signed accumulator register A
>>   * establish a PWM cycle length, N clock cycles
>>   * have a "desired output" value V
>>   * on each clock cycle, accumulate A = A + V, and then...
>>     - if A is negative, supply 0 as the output
>>     - if A is positive, supply 1 as the output and modify
>>       the accumulator by forming A = A - N
>>
>
>

-- 
%  Randy Yates                  % "Midnight, on the water... 
%% Fuquay-Varina, NC            %  I saw...  the ocean's daughter." 
%%% 919-577-9882                % 'Can't Get It Out Of My Head' 
%%%% <yates@ieee.org>           % *El Dorado*, Electric Light Orchestra
http://home.earthlink.net/~yatescr

Or other people querying on this and related topics -- Don't overlook
substantive tutorial material posted on the Usenet over the years, some of
it separately WWW-archived (though some of it is semi-technical
explanations, partly to answer nonsense fermenting in some audio
applications).  A 1991 example can be found in stand-alone archive at
various sites such as

http://members.chello.nl/~m.heijligers/DAChtml/Digital%20Theory/hauser.txt

or by searching for the set of words "oversampling curious furious damned."
(Its predecessor was a 1987 Usenet tutorial.)

I also wrote among other things the standard JAES tutorial-review paper on
the subject, in 1991, which the AES will email you instantly via

http://www.aes.org/journal/search.html

-- enter keyword phrase "Principles of Oversampling" to locate the paper.

The AES charges $5 for such reprints (by email or paper); in this case the
page count makes it a relative bargain per page.  It does include the basic
classes of oversampling-quantizer structures in block-diagram form.  Many
people have commented over the years on the tutorial benefit that they got
from that paper.  Few other tutorials address explicitly the overlap of
quantization and antialias filtering functions or the conflicts of technical
"cultures" and languages that pervade the literature (the language issues
have worsened since then, by the way).  This paper is in steady use as
teaching material at MIT; even a few other authors in the JAES have read it
;-).  (Also, it's a matter of record that many firms and people saw my
seminars on this topic before they later wrote on it themselves or offered
products:  Analog Devices, Burr-Brown, GE-Intersil, IBM, National
Semiconductor, Texas Instruments, Cal Tech, Robert M. Gray, Gabor Temes,
many others.)

In case this is helpful.     --  Max Hauser

Hi Randy,
Thanks for the reply and book recommendation, much appreciated.
So, for a second order modulator, this is the algorithm?

* maintain a signed accumulator registers A, B
* establish a PWM cycle length, N clock cycles
* have a "desired output" value V
* on each clock cycle, accumulate A = A + V, B = B + A and then...
     - if B is negative, supply 0 as the output
     - if B is positive, supply 1 as the output and modify
       the A accumulator by forming A = A - N

Thanks again, Syms.

"Randy Yates" <yates@ieee.org> wrote in message
news:smewwyvm.fsf@ieee.org...
> Hey Symon,
>
> An Lth-order modulator yields a noise transfer function of H(z) =
> (1-z^(-1))^L. The power response of this is |H(\omega)|^2 = [2*(1 -
> cos(\omega))]^L.
>
> Note this is for a cascade of simple integrators in the modulator
> loop. More sophisticated transfer functions can be constructed.
>
> I recommend the following reference:
>
> @BOOK{deltasigmadataconverters,
>   title = "Delta-Sigma Data Converters: Theory, Design, and Simulation",
>   author = "{Steven~R.~Norsworthy,} {Richard~Schreier,} and
{Gabor~C.~Temes}",
>   publisher = "IEEE Press",
>   year = "1997"}
>
> Also note that there is a survey of delta sigma techniques in the current
issue
> of the Journal of the Audio Engineering Society.
>
> --Randy
>

"Max Hauser" <maxREMOVE@THIStdl.com> wrote in message
news:108eo2v4v38nu90@corp.supernews.com...
> or by searching for the set of words "oversampling curious furious
damned."
> (Its predecessor was a 1987 Usenet tutorial.)
>
I must admit, that's one set of words I didn't try....
>
> In case this is helpful.     --  Max Hauser
>
Very much so, thanks Max,
Syms.

Hmmm, thinking about it, I may've missed off B = B - 2N at the end. I must
do some simulations later.
Cheers, Syms.
"Symon" <symon_brewer@hotmail.com> wrote in message
news:c68skc$9fj6d$1@ID-212844.news.uni-berlin.de...
> Hi Randy,
> Thanks for the reply and book recommendation, much appreciated.
> So, for a second order modulator, this is the algorithm?
>
> * maintain a signed accumulator registers A, B
> * establish a PWM cycle length, N clock cycles
> * have a "desired output" value V
> * on each clock cycle, accumulate A = A + V, B = B + A and then...
>      - if B is negative, supply 0 as the output
>      - if B is positive, supply 1 as the output and modify
>        the A accumulator by forming A = A - N
>
> Thanks again, Syms.
>
> "Randy Yates" <yates@ieee.org> wrote in message
> news:smewwyvm.fsf@ieee.org...
> > Hey Symon,
> >
> > An Lth-order modulator yields a noise transfer function of H(z) =
> > (1-z^(-1))^L. The power response of this is |H(\omega)|^2 = [2*(1 -
> > cos(\omega))]^L.
> >
> > Note this is for a cascade of simple integrators in the modulator
> > loop. More sophisticated transfer functions can be constructed.
> >
> > I recommend the following reference:
> >
> > @BOOK{deltasigmadataconverters,
> >   title = "Delta-Sigma Data Converters: Theory, Design, and Simulation",
> >   author = "{Steven~R.~Norsworthy,} {Richard~Schreier,} and
> {Gabor~C.~Temes}",
> >   publisher = "IEEE Press",
> >   year = "1997"}
> >
> > Also note that there is a survey of delta sigma techniques in the
current
> issue
> > of the Journal of the Audio Engineering Society.
> >
> > --Randy
> >
>
>

"Symon" <symon_brewer@hotmail.com> writes:

> Hi Randy,
> Thanks for the reply and book recommendation, much appreciated.
> So, for a second order modulator, this is the algorithm?
> 
> * maintain a signed accumulator registers A, B
> * establish a PWM cycle length, N clock cycles
> * have a "desired output" value V
> * on each clock cycle, accumulate A = A + V, B = B + A and then...
>      - if B is negative, supply 0 as the output
>      - if B is positive, supply 1 as the output and modify
>        the A accumulator by forming A = A - N
> 
> Thanks again, Syms.

Hi Syms,

The above pseudo-code isn't right - you must subtract the output
from the input before accumulating (integrating). Try this:

% Initialize:
i = 0   % first integrator
j = 0   % second integrator
y = 0   % output

% Loop
for n = 0 to infinity
  d[n] = x[n] - y[n-1]
  i[n] = d[n] + i[n-1]
  j[n] = i[n] + j[n-1]
  y[n] = Q(j[n])
end

The Q() function is the quantizer function, which can be as
you described above. Note that the operation you described
gives you a DC offset, but that's OK. 

I'm not sure what your "PWM cycle length" is about. Delta
sigma modulation is NOT PWM. You also haven't yet mentioned
whether this is an A/D or a D/A. What I've given is a "D/D",
which is essentially a D/A, where you have to upsample the
input data first to the desired oversampling ratio.

Does this make sense? Please ask more questions if not.

--Randy


> 
> "Randy Yates" <yates@ieee.org> wrote in message
> news:smewwyvm.fsf@ieee.org...
> > Hey Symon,
> >
> > An Lth-order modulator yields a noise transfer function of H(z) =
> > (1-z^(-1))^L. The power response of this is |H(\omega)|^2 = [2*(1 -
> > cos(\omega))]^L.
> >
> > Note this is for a cascade of simple integrators in the modulator
> > loop. More sophisticated transfer functions can be constructed.
> >
> > I recommend the following reference:
> >
> > @BOOK{deltasigmadataconverters,
> >   title = "Delta-Sigma Data Converters: Theory, Design, and Simulation",
> >   author = "{Steven~R.~Norsworthy,} {Richard~Schreier,} and
> {Gabor~C.~Temes}",
> >   publisher = "IEEE Press",
> >   year = "1997"}
> >
> > Also note that there is a survey of delta sigma techniques in the current
> issue
> > of the Journal of the Audio Engineering Society.
> >
> > --Randy
> >
> 
> 

-- 
Randy Yates
Sony Ericsson Mobile Communications
Research Triangle Park, NC, USA
randy.yates@sonyericsson.com, 919-472-1124

"Randy Yates" <randy.yates@sonyericsson.com> wrote in message
news:xxpn05394ok.fsf@usrts005.corpusers.net...
>
> I'm not sure what your "PWM cycle length" is about. Delta
> sigma modulation is NOT PWM. You also haven't yet mentioned
> whether this is an A/D or a D/A. What I've given is a "D/D",
> which is essentially a D/A, where you have to upsample the
> input data first to the desired oversampling ratio.
>
> Does this make sense? Please ask more questions if not.
>
> --Randy

Hi Randy,
Yeah, the mists are starting to clear! My next step will be to do some
simulations/experiments!
The application I'm thinking about is for implementing the fractional-N
feedback divider in a fractional-N phase locked loop. The feedback divider
output is a single bit (which controls a phase comparator charge pump, which
feeds a charge integrator via a LP filter, which controls a VCO), but I'm
thinking about how to shape the noise in this signal, specifically to move
the noise to a higher frequency.
Thanks again, Syms.

"Symon" <symon_brewer@hotmail.com> writes:

> "Randy Yates" <randy.yates@sonyericsson.com> wrote in message
> news:xxpn05394ok.fsf@usrts005.corpusers.net...
>>
>> I'm not sure what your "PWM cycle length" is about. Delta
>> sigma modulation is NOT PWM. You also haven't yet mentioned
>> whether this is an A/D or a D/A. What I've given is a "D/D",
>> which is essentially a D/A, where you have to upsample the
>> input data first to the desired oversampling ratio.
>>
>> Does this make sense? Please ask more questions if not.
>>
>> --Randy
>
> Hi Randy,
> Yeah, the mists are starting to clear! My next step will be to do some
> simulations/experiments!

Sounds like the perfect thing to do at this stage.

> The application I'm thinking about is for implementing the fractional-N
> feedback divider in a fractional-N phase locked loop. The feedback divider
> output is a single bit (which controls a phase comparator charge pump, which
> feeds a charge integrator via a LP filter, which controls a VCO), but I'm
> thinking about how to shape the noise in this signal, specifically to move
> the noise to a higher frequency.

Sounds like a perfect application! Have fun!
-- 
%  Randy Yates                  % "And all that I can do
%% Fuquay-Varina, NC            %  is say I'm sorry, 
%%% 919-577-9882                %  that's the way it goes..."
%%%% <yates@ieee.org>           % Getting To The Point', *Balance of Power*, ELO
http://home.earthlink.net/~yatescr

"Symon" <symon_brewer@hotmail.com> wrote in message
news:c69h5s$9dr4v$1@ID-212844.news.uni-berlin.de...
>
> "Randy Yates" <randy.yates@sonyericsson.com> wrote in message
> news:xxpn05394ok.fsf@usrts005.corpusers.net...
> >
> > I'm not sure what your "PWM cycle length" is about. Delta
> > sigma modulation is NOT PWM. You also haven't yet mentioned
> > whether this is an A/D or a D/A. What I've given is a "D/D",
> > which is essentially a D/A, where you have to upsample the
> > input data first to the desired oversampling ratio.
> >
> > Does this make sense? Please ask more questions if not.
> >
> > --Randy
>
> Hi Randy,
> Yeah, the mists are starting to clear! My next step will be to do
some
> simulations/experiments!
> The application I'm thinking about is for implementing the
fractional-N
> feedback divider in a fractional-N phase locked loop. The feedback
divider
> output is a single bit (which controls a phase comparator charge
pump, which
> feeds a charge integrator via a LP filter, which controls a VCO),
but I'm
> thinking about how to shape the noise in this signal, specifically
to move
> the noise to a higher frequency.
> Thanks again, Syms.
>
>
Google is your friend: as well as the obvious keywords to search on,
try entering "multiple modulator" in the google exact phrase box,
and "fractional" in the all words box.

Regards
    Ian