Demodulating AM pulse width coding (long post)

I am decoding an IRIG-B signal in an FPGA.  The signal is 100 bps
encoded with pulse width with three levels (0, 1, position identifier)
and modulated in AM on a 1 kHz carrier.  The AM is typically 3:1
amplitude ratio between the mark and the space.

I am thinking about demodulating the AM by analyzing the carrier a
single cycle at a time, starting with the zero crossing point.  Using
the samples from an ADC, the carrier amplitude will be measured using
a correlation to a cycle of a reference 1 kHz sine wave.  I believe
this is the same thing as performing a DFT on the one bin of 1 kHz.
The resulting value is related to the amplitude of the carrier.

I did some simple simulations using excel to see what error is
introduced by a phase misalignment.  I am sampling at 8 kHz, so the
initial phase mismatch will be +-22.5 degrees using a reference with
the first sample at 22.5 degrees.  The sampling clock is not phase
locked to the input signal, but it will be crystal controlled.  The
phase mismatch resulted in a relatively low amplitude error (1.08
between the highest and lowest).  Adding in -6 dB of randomly
distributed noise, the measured amplitude for a cycle ranges over a
ratio of 1.5 most of the time.  Given the 3x modulation factor, this
seems adequate.

To allow for the difference in clock speed, at the end of each cycle
of the carrier, the correlator will resync to the positive going zero
crossing.  This will require that I keep the last sample of the
previous cycle because it may also be the first sample of the next
cycle if the zero has just been crossed.

I plan to set the threshold of the level detector using a low pass
filter of the form Y1 = (1-a)Yi-1 + aXi.  I will set 'a' so that it
takes some 1000 cycles to make a 10% movement of the mean.  I expect I
will need to scale Y to compensate for the fact that the modulated
pulse width is not 50/50 duty cycle on the average.  The 0 pulse is 2
cycles of high AM and 8 cycles of low AM.  The 1 pulse is 5 cycles of
high AM and 5 of low AM.  The position identifier pulse (first of
frame and last of each 10 pulses) is 8 cycles of high AM and 2 low
AM.

The pulse width will be decoded by counting the number of high and low
cycles.  There will be some accounting for single cycle errors, e.g.
if the pattern over 10 cycles is 2 high, 1 low, 2 high and 5 low, this
will be decoded as a 1 and not a 0.  I see this as a digital match,
similar to the analog correlation.  Each series of 10 cycles will be
XORed with three reference patterns (0, 1, ref) producing three
numerical results.  The highest one is considered the match.

I think this will provide a robust demodulation along with a good
decode of the pulse width and also preserve exact timing (to the ADC
sample) of the zero crossing which is the exact time reference.

Does anyone see a problem with this?  Is any part of this overly
complicated?

One area I am not sure about is the low pass filter on the detector.
A single message is a second long. The average amplitude will vary
message by message.  I would like the threshold to adjust very slowly
once it is "in the range" so that it does not wander much from message
to message.  But this might result in a filter that will take many
seconds to initially lock in.

Is it uncommon to design a filter that adjusts more quickly with
larger errors and more slowly when the current output is near the next
output?  Since the input samples range over a wide +- range by design,
I am not certain how I might do this.

On Sat, 26 Apr 2008 16:18:29 -0700, rickman wrote:

> I am decoding an IRIG-B signal in an FPGA.  The signal is 100 bps
> encoded with pulse width with three levels (0, 1, position identifier)
> and modulated in AM on a 1 kHz carrier.  The AM is typically 3:1
> amplitude ratio between the mark and the space.
> 
> I am thinking about demodulating the AM by analyzing the carrier a
> single cycle at a time, starting with the zero crossing point.  Using
> the samples from an ADC, the carrier amplitude will be measured using a
> correlation to a cycle of a reference 1 kHz sine wave.  I believe this
> is the same thing as performing a DFT on the one bin of 1 kHz. The
> resulting value is related to the amplitude of the carrier.
> 
> I did some simple simulations using excel to see what error is
> introduced by a phase misalignment.  I am sampling at 8 kHz, so the
> initial phase mismatch will be +-22.5 degrees using a reference with the
> first sample at 22.5 degrees.  The sampling clock is not phase locked to
> the input signal, but it will be crystal controlled.  The phase mismatch
> resulted in a relatively low amplitude error (1.08 between the highest
> and lowest).  Adding in -6 dB of randomly distributed noise, the
> measured amplitude for a cycle ranges over a ratio of 1.5 most of the
> time.  Given the 3x modulation factor, this seems adequate.
> 
> To allow for the difference in clock speed, at the end of each cycle of
> the carrier, the correlator will resync to the positive going zero
> crossing.  This will require that I keep the last sample of the previous
> cycle because it may also be the first sample of the next cycle if the
> zero has just been crossed.
> 
> I plan to set the threshold of the level detector using a low pass
> filter of the form Y1 = (1-a)Yi-1 + aXi.  I will set 'a' so that it
> takes some 1000 cycles to make a 10% movement of the mean.  I expect I
> will need to scale Y to compensate for the fact that the modulated pulse
> width is not 50/50 duty cycle on the average.  The 0 pulse is 2 cycles
> of high AM and 8 cycles of low AM.  The 1 pulse is 5 cycles of high AM
> and 5 of low AM.  The position identifier pulse (first of frame and last
> of each 10 pulses) is 8 cycles of high AM and 2 low AM.
> 
> The pulse width will be decoded by counting the number of high and low
> cycles.  There will be some accounting for single cycle errors, e.g. if
> the pattern over 10 cycles is 2 high, 1 low, 2 high and 5 low, this will
> be decoded as a 1 and not a 0.  I see this as a digital match, similar
> to the analog correlation.  Each series of 10 cycles will be XORed with
> three reference patterns (0, 1, ref) producing three numerical results. 
> The highest one is considered the match.
> 
> I think this will provide a robust demodulation along with a good decode
> of the pulse width and also preserve exact timing (to the ADC sample) of
> the zero crossing which is the exact time reference.
> 
> Does anyone see a problem with this?  Is any part of this overly
> complicated?
> 
> One area I am not sure about is the low pass filter on the detector. A
> single message is a second long. The average amplitude will vary message
> by message.  I would like the threshold to adjust very slowly once it is
> "in the range" so that it does not wander much from message to message. 
> But this might result in a filter that will take many seconds to
> initially lock in.
> 
> Is it uncommon to design a filter that adjusts more quickly with larger
> errors and more slowly when the current output is near the next output? 
> Since the input samples range over a wide +- range by design, I am not
> certain how I might do this.

I can see a lot of different approaches to this problem, and which one is 
'best' depends greatly on your circumstances.  I don't think your 
approach is bad in itself, but it may be overly complicated and it will 
only work well in a low-noise environment (in particular I suspect that 
your synchronization method is weak).

You may find it more useful to only filter the values of '1' pulses, and 
set your threshold to 2/3 the '1' level.  This will make your filter 
fairly immune to the distribution of ones and zeros within a message, and 
should give you a more consistent threshold once it has latched on to the 
right threshold value.  If that algorithm gets confused by too many 
zeros, then consider using a pair of envelope detectors to separately 
track the '1' and '0' levels, and set your threshold between them.

Tracking the carrier phase with a PLL will make the system much more 
robust to noise (zero crossing methods tend to enhance noise), assuming 
that the carrier phase doesn't change much with time.  Ditto tracking the 
data timing with a PLL.  If you track both sets of timing with PLLs then 
you can make a nice set of three matched filters to the three data 
symbols, and get yourself a near-optimal demodulator in the presence of 
noise.

If acquisition time is important and you have processing power to throw 
at the problem you can sample the data a second (or two or three) in 
advance and process it in advance for the synchronization information, 
then process it again to extract the data.  This would give you about the 
same performance as my PLL suggestion above, but it'd give you just as 
good of reception of the very first message as all the rest of them 
(assuming all but the noisiest of environments).

-- 
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com

Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html

Thanks for the reply.  It is nice to be able to bounce ideas off of
someone.

On Apr 27, 5:17 pm, Tim Wescott <t...@seemywebsite.com> wrote:
>
> I can see a lot of different approaches to this problem, and which one is
> 'best' depends greatly on your circumstances.  I don't think your
> approach is bad in itself, but it may be overly complicated and it will
> only work well in a low-noise environment (in particular I suspect that
> your synchronization method is weak).
>
> You may find it more useful to only filter the values of '1' pulses, and
> set your threshold to 2/3 the '1' level.  This will make your filter
> fairly immune to the distribution of ones and zeros within a message, and
> should give you a more consistent threshold once it has latched on to the
> right threshold value.  If that algorithm gets confused by too many
> zeros, then consider using a pair of envelope detectors to separately
> track the '1' and '0' levels, and set your threshold between them.

I have not analyzed the message in detail, but the general case
guarantees at least 25% low cycles because of the protocol.  There are
15 out of the 100 bits that are always zeros with only 20% high
cycles.  It looks like once a year 47 of the data bits are zeros with
20% high cycles.  So there will be cases where less than a third of
the carrier cycles are high and a low pass filter on the average won't
sufficiently smooth them out.

I'm not sure what you mean by "a pair of envelope detectors".  If you
mean I should have two averaging circuits, one for the highs and one
for the lows, I can see that working ok.  I would then split the
difference to get the threshold.  That would not be too hard to
implement.


> Tracking the carrier phase with a PLL will make the system much more
> robust to noise (zero crossing methods tend to enhance noise), assuming
> that the carrier phase doesn't change much with time.  Ditto tracking the
> data timing with a PLL.  If you track both sets of timing with PLLs then
> you can make a nice set of three matched filters to the three data
> symbols, and get yourself a near-optimal demodulator in the presence of
> noise.

The sensitivity of the zero crossing to noise did occur to me as I was
making the post.  My simulation did not account for that.  When you
refer to low noise, can you put a dB figure on that?  I am sure the
customer will be happy with this working in a 10 dB SNR environment.

I can design a digital PLL if I need to.  But the first pass will not
use the PLL since I have to get something working in about two weeks.
Then I have a month or so to tweak the design to work better.  I can
add a PLL then.

I can't say I understand your description of tracking "both sets of
timing".  Do you mean to have a PLL for the carrier as well as a PLL
for the data?  The carrier and data are synchronous at 10:1.  If I am
tracking the carrier, then all I have to do is sync to the data pulses
and I should be good.


> If acquisition time is important and you have processing power to throw
> at the problem you can sample the data a second (or two or three) in
> advance and process it in advance for the synchronization information,
> then process it again to extract the data.  This would give you about the
> same performance as my PLL suggestion above, but it'd give you just as
> good of reception of the very first message as all the rest of them
> (assuming all but the noisiest of environments).

I can't say I understand this at all.  The messages are real time by
definition since it is a time code.  I have to decode the bits and
pass them on as quickly as I receive them.  I can take some time to
lock into the signal, but once locked, I can't buffer messages to
process them.

Thanks for your comments.  I appreciate it.

Rick

rickman wrote:
> Thanks for your comments.  I appreciate it.
> 

I was involved in an IRIG-B demod about 20 years ago.  As I recall, the 
first thing we did was to remove DC, then square the signal, and run 
that through a 2KHz notch filter.  Since IRIG-B is primarily a 1KHz 
signal, squaring produced a double frequency component (the sum), and a 
DC component (the difference).  The notch filter IIRC, was a 4-tap 
boxcar (really a comb), and that knocked out the double-freq component. 
  We had a nice square wave at the output of the notch filter, which we 
then needed to slice and dice to get the ones, zeros, and position pulses.

HTH.

On Apr 28, 10:07 am, Jim Thomas <jtho...@bittware.com> wrote:
> rickman wrote:
> > Thanks for your comments.  I appreciate it.
>
> I was involved in an IRIG-B demod about 20 years ago.  As I recall, the
> first thing we did was to remove DC, then square the signal, and run
> that through a 2KHz notch filter.  Since IRIG-B is primarily a 1KHz
> signal, squaring produced a double frequency component (the sum), and a
> DC component (the difference).  The notch filter IIRC, was a 4-tap
> boxcar (really a comb), and that knocked out the double-freq component.
>   We had a nice square wave at the output of the notch filter, which we
> then needed to slice and dice to get the ones, zeros, and position pulses.

That is interesting.  Was the 4 tap comb just a running sum of the
last four samples?  If you were sampling at 8 kHz that would give you
a full cycle of the frequency doubled carrier and would give you
square waves with a rise time of one clock cycle.

In terms of processing, this is the same as what I was doing; squaring
the incoming signal vs. multiplying it by a reference carrier followed
by a sum over a carrier cycle.  I am planning to sync to the zero
crossing when calculating the sum.  Then instead of getting 8 values
per cycle, I get one and the rise time is one sample.

I suppose using the squared input eliminates the need to sync to the
carrier, but I have to do that anyway since the carrier is part of the
timing reference.  The PLL gives me a reference, phase locked to the
carrier, that I can use to determine the zero crossing of the carrier,
without interference from the noise.  I guess I can combine both
methods.  Use the PLL to provide the phase reference and use the
squared signal to measure the amplitude.

I'm a little confused. As I understand IRIG-B, it is _either_ modulated
onto a 1kHz carrier _or_ it is pulse-width modulated DC - not both. There
is more information about IRIG here: 

http://www.meinberg.de/english/info/irig.htm

Are you talking about IRIG-B 123? That's one of the most common ones, but
it is amplitude modulated, not pulse-width modulated.

I wouldn't bother with correlating it, low-pass filtering it, or anything
else. Ignoring all of the stuff to be done _after_ you work it out into
binary, the actual sinusoid-to-binary conversion could be done by reading
in an initial 20-30 samples and measuring two or three local maxes to
figure out approximately what phase your signal is coming in at.

Once you find a maxima, you can keep track of which of your 8 samples it's
coming in on, since each carrier cycle's maxima will always occur in the
same sample place unless the incoming phase changes or you change your
sampling phase.

Although you probaby won't hit the precise peak of your 1kHz sinusoid this
way, with 8 samples per cycle you're guaranteed to be close enough to your
maximum that you can tell the difference.

Then you can just read the value every 8 samples (starting at whatever
sample you determined to be your maxima) and make an amplitude-based
decision about whether that particular cycle is a binary '1' or a '0'.


-Nick


>I am decoding an IRIG-B signal in an FPGA.  The signal is 100 bps
>encoded with pulse width with three levels (0, 1, position identifier)
>and modulated in AM on a 1 kHz carrier.  The AM is typically 3:1
>amplitude ratio between the mark and the space.
>
>I am thinking about demodulating the AM by analyzing the carrier a
>single cycle at a time, starting with the zero crossing point.  Using
>the samples from an ADC, the carrier amplitude will be measured using
>a correlation to a cycle of a reference 1 kHz sine wave.  I believe
>this is the same thing as performing a DFT on the one bin of 1 kHz.
>The resulting value is related to the amplitude of the carrier.
>
>I did some simple simulations using excel to see what error is
>introduced by a phase misalignment.  I am sampling at 8 kHz, so the
>initial phase mismatch will be +-22.5 degrees using a reference with
>the first sample at 22.5 degrees.  The sampling clock is not phase
>locked to the input signal, but it will be crystal controlled.  The
>phase mismatch resulted in a relatively low amplitude error (1.08
>between the highest and lowest).  Adding in -6 dB of randomly
>distributed noise, the measured amplitude for a cycle ranges over a
>ratio of 1.5 most of the time.  Given the 3x modulation factor, this
>seems adequate.
>
>To allow for the difference in clock speed, at the end of each cycle
>of the carrier, the correlator will resync to the positive going zero
>crossing.  This will require that I keep the last sample of the
>previous cycle because it may also be the first sample of the next
>cycle if the zero has just been crossed.
>
>I plan to set the threshold of the level detector using a low pass
>filter of the form Y1 = (1-a)Yi-1 + aXi.  I will set 'a' so that it
>takes some 1000 cycles to make a 10% movement of the mean.  I expect I
>will need to scale Y to compensate for the fact that the modulated
>pulse width is not 50/50 duty cycle on the average.  The 0 pulse is 2
>cycles of high AM and 8 cycles of low AM.  The 1 pulse is 5 cycles of
>high AM and 5 of low AM.  The position identifier pulse (first of
>frame and last of each 10 pulses) is 8 cycles of high AM and 2 low
>AM.
>
>The pulse width will be decoded by counting the number of high and low
>cycles.  There will be some accounting for single cycle errors, e.g.
>if the pattern over 10 cycles is 2 high, 1 low, 2 high and 5 low, this
>will be decoded as a 1 and not a 0.  I see this as a digital match,
>similar to the analog correlation.  Each series of 10 cycles will be
>XORed with three reference patterns (0, 1, ref) producing three
>numerical results.  The highest one is considered the match.
>
>I think this will provide a robust demodulation along with a good
>decode of the pulse width and also preserve exact timing (to the ADC
>sample) of the zero crossing which is the exact time reference.
>
>Does anyone see a problem with this?  Is any part of this overly
>complicated?
>
>One area I am not sure about is the low pass filter on the detector.
>A single message is a second long. The average amplitude will vary
>message by message.  I would like the threshold to adjust very slowly
>once it is "in the range" so that it does not wander much from message
>to message.  But this might result in a filter that will take many
>seconds to initially lock in.
>
>Is it uncommon to design a filter that adjusts more quickly with
>larger errors and more slowly when the current output is near the next
>output?  Since the input samples range over a wide +- range by design,
>I am not certain how I might do this.
>

On Apr 30, 9:05 pm, "nrclark" <nicholas.cl...@gmail.com> wrote:
> I'm a little confused. As I understand IRIG-B, it is _either_ modulated
> onto a 1kHz carrier _or_ it is pulse-width modulated DC - not both. There
> is more information about IRIG here:
>
> http://www.meinberg.de/english/info/irig.htm
>
> Are you talking about IRIG-B 123? That's one of the most common ones, but
> it is amplitude modulated, not pulse-width modulated.

I am talking about IRIG-B 120.  The "trit" is coded into a pulse
width, either 2, 5 or 8 mS long with a 10 mS period.  100 of these
"trits" make up a 1 second time message.  The pulses are then
modulated onto a 1 kHz, synchronized carrier as AM with a modulation
of between 3:1 and 6:1.  I am working from the "IRIG STANDARD 200-04,
IRIG SERIAL TIME CODE FORMATS" document, dated SEPTEMBER 2004,
prepared by the TIMING COMMITTEE TELECOMMUNICATIONS AND TIMING GROUP
RANGE COMMANDERS COUNCIL with a full pages of other participating DOD
groups.  I don't recall where I found this, but they say it can be
downloaded at http://jcs.mil/RCC.

If you have this document, turn to page 4-8, figure 4-2.  It shows all
three modulation options together.  Format B0xx, PWM is essentially an
unmodulated signal while B1xx is AM of the PWM and B2xx is Manchester
encoded PWM.  At least that is the way I see it.  If you demodulate
the AM, you get the PWM signal, not bits.  The same is true for the
Manchester signal because it is 10x the bit rate and also returns the
PWM in a digital form 10x oversampled.


> I wouldn't bother with correlating it, low-pass filtering it, or anything
> else. Ignoring all of the stuff to be done _after_ you work it out into
> binary, the actual sinusoid-to-binary conversion could be done by reading
> in an initial 20-30 samples and measuring two or three local maxes to
> figure out approximately what phase your signal is coming in at.
>
> Once you find a maxima, you can keep track of which of your 8 samples it's
> coming in on, since each carrier cycle's maxima will always occur in the
> same sample place unless the incoming phase changes or you change your
> sampling phase.

Hmmm... but if my master frequency is not *exactly* the a multiple of
the time code, my phase will vary continuously.  Of course, I could
use a PLL to sync my sample clock to the carrier, but I did not
include one capable of driving the CODEC.  I may need a DPLL, but it
will be to create the ref carrier (1 kHz) to support the demodulation,
not the sample clock which is driven from a 12.288 MHz clock.

I think the low-pass filter and correlation are needed if the signal
is not perfectly clean.  My initial concept was to find the peaks to
detect the phase and amplitude of the AM signal.  But I realized that
this would not be very robust in the presence of noise.  The
correlation is a good way to effectively filter and average (in a
weighted manner) the 8 samples of a single cycle.  My zero crossing
detector based on the incoming signal is still sensitive to noise as
Tim pointed out.  Using a DPLL to sync the sample clock to the carrier
would greatly reduce the sensitivity of the zero crossing to noise.


> Although you probaby won't hit the precise peak of your 1kHz sinusoid this
> way, with 8 samples per cycle you're guaranteed to be close enough to your
> maximum that you can tell the difference.

Yes, I realize that.  But the correlation, whether it is auto or to a
reference, it much more robust when there is noise.  I don't want my
board to fail where others don't.  Of course, my first pass is due out
next week and it won't have any bells or whistles.  It will just work
enough to support the software people.


> Then you can just read the value every 8 samples (starting at whatever
> sample you determined to be your maxima) and make an amplitude-based
> decision about whether that particular cycle is a binary '1' or a '0'.

Thanks for your input.  I appreciate all opinions.  When working
alone, sometimes it can be hard to judge how good of a solution you
come up with, either not good enough or maybe too good as you seem to
be saying.  I like getting feedback, pro or con... in fact it is
usually much more educational to get constructive criticism.  I have
learned a few things doing this design, mainly in the opamp driver
circuit.  It was tough making that work in the tiny space I had
available.


Rick

On Apr 30, 9:00 pm, rickman <gnu...@gmail.com> wrote:
> On Apr 30, 9:05 pm, "nrclark" <nicholas.cl...@gmail.com> wrote:
>
> > I'm a little confused. As I understand IRIG-B, it is _either_ modulated
> > onto a 1kHz carrier _or_ it is pulse-width modulated DC - not both. There
> > is more information about IRIG here:
>
> >http://www.meinberg.de/english/info/irig.htm
>
> > Are you talking about IRIG-B 123? That's one of the most common ones, but
> > it is amplitude modulated, not pulse-width modulated.
>
> I am talking about IRIG-B 120.  The "trit" is coded into a pulse
> width, either 2, 5 or 8 mS long with a 10 mS period.  100 of these
> "trits" make up a 1 second time message.  The pulses are then
> modulated onto a 1 kHz, synchronized carrier as AM with a modulation
> of between 3:1 and 6:1.  I am working from the "IRIG STANDARD 200-04,
> IRIG SERIAL TIME CODE FORMATS" document, dated SEPTEMBER 2004,
> prepared by the TIMING COMMITTEE TELECOMMUNICATIONS AND TIMING GROUP
> RANGE COMMANDERS COUNCIL with a full pages of other participating DOD
> groups.  I don't recall where I found this, but they say it can be
> downloaded athttp://jcs.mil/RCC.
>
> If you have this document, turn to page 4-8, figure 4-2.  It shows all
> three modulation options together.  Format B0xx, PWM is essentially an
> unmodulated signal while B1xx is AM of the PWM and B2xx is Manchester
> encoded PWM.  At least that is the way I see it.  If you demodulate
> the AM, you get the PWM signal, not bits.  The same is true for the
> Manchester signal because it is 10x the bit rate and also returns the
> PWM in a digital form 10x oversampled.
>
> > I wouldn't bother with correlating it, low-pass filtering it, or anything
> > else. Ignoring all of the stuff to be done _after_ you work it out into
> > binary, the actual sinusoid-to-binary conversion could be done by reading
> > in an initial 20-30 samples and measuring two or three local maxes to
> > figure out approximately what phase your signal is coming in at.
>
> > Once you find a maxima, you can keep track of which of your 8 samples it's
> > coming in on, since each carrier cycle's maxima will always occur in the
> > same sample place unless the incoming phase changes or you change your
> > sampling phase.
>
> Hmmm... but if my master frequency is not *exactly* the a multiple of
> the time code, my phase will vary continuously.  Of course, I could
> use a PLL to sync my sample clock to the carrier, but I did not
> include one capable of driving the CODEC.  I may need a DPLL, but it
> will be to create the ref carrier (1 kHz) to support the demodulation,
> not the sample clock which is driven from a 12.288 MHz clock.
>
> I think the low-pass filter and correlation are needed if the signal
> is not perfectly clean.  My initial concept was to find the peaks to
> detect the phase and amplitude of the AM signal.  But I realized that
> this would not be very robust in the presence of noise.  The
> correlation is a good way to effectively filter and average (in a
> weighted manner) the 8 samples of a single cycle.  My zero crossing
> detector based on the incoming signal is still sensitive to noise as
> Tim pointed out.  Using a DPLL to sync the sample clock to the carrier
> would greatly reduce the sensitivity of the zero crossing to noise.
>
> > Although you probaby won't hit the precise peak of your 1kHz sinusoid this
> > way, with 8 samples per cycle you're guaranteed to be close enough to your
> > maximum that you can tell the difference.
>
> Yes, I realize that.  But the correlation, whether it is auto or to a
> reference, it much more robust when there is noise.  I don't want my
> board to fail where others don't.  Of course, my first pass is due out
> next week and it won't have any bells or whistles.  It will just work
> enough to support the software people.
>
> > Then you can just read the value every 8 samples (starting at whatever
> > sample you determined to be your maxima) and make an amplitude-based
> > decision about whether that particular cycle is a binary '1' or a '0'.
>
> Thanks for your input.  I appreciate all opinions.  When working
> alone, sometimes it can be hard to judge how good of a solution you
> come up with, either not good enough or maybe too good as you seem to
> be saying.  I like getting feedback, pro or con... in fact it is
> usually much more educational to get constructive criticism.  I have
> learned a few things doing this design, mainly in the opamp driver
> circuit.  It was tough making that work in the tiny space I had
> available.
>
> Rick

The Range Commanders site currently seems to be:

https://wsmrc2vger.wsmr.army.mil/rcc/

And the documents are at:

https://wsmrc2vger.wsmr.army.mil/rcc/PUBS/pubs.htm

Dale B. Dalrymple
http://dbdimages.com

rickman wrote:
> On Apr 28, 10:07 am, Jim Thomas <jtho...@bittware.com> wrote:
>> rickman wrote:
>>> Thanks for your comments.  I appreciate it.
>> I was involved in an IRIG-B demod about 20 years ago.  As I recall, the
>> first thing we did was to remove DC, then square the signal, and run
>> that through a 2KHz notch filter.  Since IRIG-B is primarily a 1KHz
>> signal, squaring produced a double frequency component (the sum), and a
>> DC component (the difference).  The notch filter IIRC, was a 4-tap
>> boxcar (really a comb), and that knocked out the double-freq component.
>>   We had a nice square wave at the output of the notch filter, which we
>> then needed to slice and dice to get the ones, zeros, and position pulses.
> 
> That is interesting.  Was the 4 tap comb just a running sum of the
> last four samples?  If you were sampling at 8 kHz that would give you
> a full cycle of the frequency doubled carrier and would give you
> square waves with a rise time of one clock cycle.

Yes, we were sampling at 8K, and the 4-tap comb was a running sum.

> 
> In terms of processing, this is the same as what I was doing; squaring
> the incoming signal vs. multiplying it by a reference carrier followed
> by a sum over a carrier cycle.  I am planning to sync to the zero
> crossing when calculating the sum.  Then instead of getting 8 values
> per cycle, I get one and the rise time is one sample.
> 
> I suppose using the squared input eliminates the need to sync to the
> carrier, but I have to do that anyway since the carrier is part of the
> timing reference.  The PLL gives me a reference, phase locked to the
> carrier, that I can use to determine the zero crossing of the carrier,
> without interference from the noise.  I guess I can combine both
> methods.  Use the PLL to provide the phase reference and use the
> squared signal to measure the amplitude.

On May 1, 9:03 am, Jim Thomas <jtho...@bittware.com> wrote:
> rickman wrote:
> > On Apr 28, 10:07 am, Jim Thomas <jtho...@bittware.com> wrote:
> >> rickman wrote:
> >>> Thanks for your comments.  I appreciate it.
> >> I was involved in an IRIG-B demod about 20 years ago.  As I recall, the
> >> first thing we did was to remove DC, then square the signal, and run
> >> that through a 2KHz notch filter.  Since IRIG-B is primarily a 1KHz
> >> signal, squaring produced a double frequency component (the sum), and a
> >> DC component (the difference).  The notch filter IIRC, was a 4-tap
> >> boxcar (really a comb), and that knocked out the double-freq component.
> >>   We had a nice square wave at the output of the notch filter, which we
> >> then needed to slice and dice to get the ones, zeros, and position pulses.
>
> > That is interesting.  Was the 4 tap comb just a running sum of the
> > last four samples?  If you were sampling at 8 kHz that would give you
> > a full cycle of the frequency doubled carrier and would give you
> > square waves with a rise time of one clock cycle.
>
> Yes, we were sampling at 8K, and the 4-tap comb was a running sum.
>
>
>
> > In terms of processing, this is the same as what I was doing; squaring
> > the incoming signal vs. multiplying it by a reference carrier followed
> > by a sum over a carrier cycle.  I am planning to sync to the zero
> > crossing when calculating the sum.  Then instead of getting 8 values
> > per cycle, I get one and the rise time is one sample.
>
> > I suppose using the squared input eliminates the need to sync to the
> > carrier, but I have to do that anyway since the carrier is part of the
> > timing reference.  The PLL gives me a reference, phase locked to the
> > carrier, that I can use to determine the zero crossing of the carrier,
> > without interference from the noise.  I guess I can combine both
> > methods.  Use the PLL to provide the phase reference and use the
> > squared signal to measure the amplitude.

Rereading my post, I realized that I mispoke (it's not just for
politicians anymore!).  I should have said the risetime is one cycle
of the frequency doubled sine wave.  That would be four clock cycles.
Still, that is not bad.

I have been letting this perk in my mind the last couple of days and
unfortunately I have not been able to work on it due to having to
chase problems with a board fab house.  They had some quality control
issues on my first order, but the second order for the test fixture
has been a complete disaster!  They accepted the order and then
canceled it without telling me.  So on the day I expected delivery of
the boards, I find out they had nothing for me at all!  Now I am in
the second day of trying to get the order back online and they are
being very retarded about making it work at all, much less in an
expedited manner!  I just can't believe how bad a company can be.  If
things are not straightened out by the end of the day, I will have to
place the order elsewhere and take a larger hit...

Thanks for your comments.  This has been a big help.

Rick