jitter calculation for ADC

Hello group,

How do I calculate the jitter for an ADC driven by a 125 MHZ. this 125 MHZ
is generated by a PLL circuit with 10MHz ref clock that has 10 ppm.

My question really is if the PLL circuit is driven by a clock with a
jitter x, will the output jitter be x or will it be magnified?

On Sun, 27 Apr 2008 15:38:26 -0500, ytach wrote:

> Hello group,
> 
> How do I calculate the jitter for an ADC driven by a 125 MHZ. this 125
> MHZ is generated by a PLL circuit with 10MHz ref clock that has 10 ppm.
> 
> My question really is if the PLL circuit is driven by a clock with a
> jitter x, will the output jitter be x or will it be magnified?

Do you mean "if the reference has jitter x will the output of the PLL 
have more jitter?".

The answer is "Yes."  Or "No.".  Depending on a lot of things.

A PLL can either clean up jitter (if it has a very stable oscillator 
compared to the reference and is narrow band), it can be jitter-neutral 
(if it is high bandwidth and if you're talking about time, not phase, 
jitter), or it can make jitter worse (which is, unfortunately, the 
general case).

If you know the jitter of the reference, and you know the phase noise of 
the 125MHz oscillator, if you know the transfer function of the loop 
filter and if you have quantified all of the extraneous noise effects 
then you can calculate the output jitter.

-- 
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com

Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html

>How do I calculate the jitter for an ADC driven by a 125 MHZ. this 125
MHZ
>is generated by a PLL circuit with 10MHz ref clock that has 10 ppm.

First, the spec of "10 ppm" more than likely relates to frequency
stability, not jitter.  This number is generally provided to let you know
how accurate the output tone's frequency is.  Phase noise in the reference
is one parameter you need to specify in order to determine what your
ultimate jitter will be.

Next, you'll also need to know what the specifications for the PLL,
generally given in some dBc/Hz value, and VCO are.  Both National
Semiconductor and Analog Devices have tools that will allow you to input
various parameters and plot your output phase noises.

Jitter definitions vary depending upon what you're looking for, e.g. peak
to peak, rms, etc., though rms jitter is the most common for deriving a
jitter spec in terms of an ADC (since rms jitter drives ADC noise floor).

>My question really is if the PLL circuit is driven by a clock with a
>jitter x, will the output jitter be x or will it be magnified?

The previous post is about is unambiguous as you can get... it just
depends. :)

Mark

Thank you Mark and Tim for your great answers! I would like to confirm the
following:

Do phase noise and jitter represent the same thing but the first is in
frequency domain and the second is in time domain?

By reviewing the manuals I have, I found a clock skew of 150 ps! To me, it
appears to be very high compared with what I am expecting from time jitter.
Should I consider the clock skew as a worst case value for jitter. Although
I know that the skew is static time parameter while jitter is almost
periodic but I am not sure what to do.

Mark: You are right. I am after the rms value because I want to find the
noise floor after the ADC using SNR=-20log10(2pi.fmax.jitter(rms))
In fact, my setup is 10MHz ref with 10 ppm, The synthesizer I am using is
AD9511 and the ADC is ADS5500.

Thank you all for sharing your experience in this issue.

>>How do I calculate the jitter for an ADC driven by a 125 MHZ. this 125
>MHZ
>>is generated by a PLL circuit with 10MHz ref clock that has 10 ppm.
>
>First, the spec of "10 ppm" more than likely relates to frequency
>stability, not jitter.  This number is generally provided to let you
know
>how accurate the output tone's frequency is.  Phase noise in the
reference
>is one parameter you need to specify in order to determine what your
>ultimate jitter will be.
>
>Next, you'll also need to know what the specifications for the PLL,
>generally given in some dBc/Hz value, and VCO are.  Both National
>Semiconductor and Analog Devices have tools that will allow you to input
>various parameters and plot your output phase noises.
>
>Jitter definitions vary depending upon what you're looking for, e.g.
peak
>to peak, rms, etc., though rms jitter is the most common for deriving a
>jitter spec in terms of an ADC (since rms jitter drives ADC noise
floor).
>
>>My question really is if the PLL circuit is driven by a clock with a
>>jitter x, will the output jitter be x or will it be magnified?
>
>The previous post is about is unambiguous as you can get... it just
>depends. :)
>
>Mark
>

On Apr 29, 2:25 pm, "ytach" <ytachw...@ou.edu> wrote:
> Thank you Mark and Tim for your great answers! I would like to confirm the
> following:
>
> Do phase noise and jitter represent the same thing but the first is in
> frequency domain and the second is in time domain?
>
> By reviewing the manuals I have, I found a clock skew of 150 ps! To me, it
> appears to be very high compared with what I am expecting from time jitter.
> Should I consider the clock skew as a worst case value for jitter. Although
> I know that the skew is static time parameter while jitter is almost
> periodic but I am not sure what to do.
>
> Mark: You are right. I am after the rms value because I want to find the
> noise floor after the ADC using SNR=-20log10(2pi.fmax.jitter(rms))
> In fact, my setup is 10MHz ref with 10 ppm, The synthesizer I am using is
> AD9511 and the ADC is ADS5500.
>
> Thank you all for sharing your experience in this issue.
>
>
>
> >>How do I calculate the jitter for an ADC driven by a 125 MHZ. this 125
> >MHZ
> >>is generated by a PLL circuit with 10MHz ref clock that has 10 ppm.
>
> >First, the spec of "10 ppm" more than likely relates to frequency
> >stability, not jitter.  This number is generally provided to let you
> know
> >how accurate the output tone's frequency is.  Phase noise in the
> reference
> >is one parameter you need to specify in order to determine what your
> >ultimate jitter will be.
>
> >Next, you'll also need to know what the specifications for the PLL,
> >generally given in some dBc/Hz value, and VCO are.  Both National
> >Semiconductor and Analog Devices have tools that will allow you to input
> >various parameters and plot your output phase noises.
>
> >Jitter definitions vary depending upon what you're looking for, e.g.
> peak
> >to peak, rms, etc., though rms jitter is the most common for deriving a
> >jitter spec in terms of an ADC (since rms jitter drives ADC noise
> floor).
>
> >>My question really is if the PLL circuit is driven by a clock with a
> >>jitter x, will the output jitter be x or will it be magnified?
>
> >The previous post is about is unambiguous as you can get... it just
> >depends. :)
>
> >Mark

Try some of these application notes and get values from your data
sheets:

App notes

ADI App Note 501
http://www.analog.com/UploadedFiles/Application_Notes/6386859756494064912342505447175991257024546937062255921511183854180687755AN501_a.pdf

http://www.analog.com/en/content/0,2886,761%255F795%255F91284%255F0,00.html

http://www.maxim-ic.com/appnotes.cfm/appnote_number/800/

http://gmrt.ncra.tifr.res.in/~scc/BPsamp/Undersamping_&_clk_jitter.pdf


Data sheet for

http://www.gaw.ru/pdf/TI/adc/ads5500.pdf

Dale B. Dalrymple
http://dbdimages.com

I can not thank you enough All for your help. I guess I got what I need.

Dale: Thank you for your very useful links. 

>On Apr 29, 2:25 pm, "ytach" <ytachw...@ou.edu> wrote:
>> Thank you Mark and Tim for your great answers! I would like to confirm
the
>> following:
>>
>> Do phase noise and jitter represent the same thing but the first is in
>> frequency domain and the second is in time domain?
>>
>> By reviewing the manuals I have, I found a clock skew of 150 ps! To me,
it
>> appears to be very high compared with what I am expecting from time
jitter.
>> Should I consider the clock skew as a worst case value for jitter.
Although
>> I know that the skew is static time parameter while jitter is almost
>> periodic but I am not sure what to do.
>>
>> Mark: You are right. I am after the rms value because I want to find
the
>> noise floor after the ADC using SNR=-20log10(2pi.fmax.jitter(rms))
>> In fact, my setup is 10MHz ref with 10 ppm, The synthesizer I am using
is
>> AD9511 and the ADC is ADS5500.
>>
>> Thank you all for sharing your experience in this issue.
>>
>>
>>
>> >>How do I calculate the jitter for an ADC driven by a 125 MHZ. this
125
>> >MHZ
>> >>is generated by a PLL circuit with 10MHz ref clock that has 10 ppm.
>>
>> >First, the spec of "10 ppm" more than likely relates to frequency
>> >stability, not jitter.  This number is generally provided to let you
>> know
>> >how accurate the output tone's frequency is.  Phase noise in the
>> reference
>> >is one parameter you need to specify in order to determine what your
>> >ultimate jitter will be.
>>
>> >Next, you'll also need to know what the specifications for the PLL,
>> >generally given in some dBc/Hz value, and VCO are.  Both National
>> >Semiconductor and Analog Devices have tools that will allow you to
input
>> >various parameters and plot your output phase noises.
>>
>> >Jitter definitions vary depending upon what you're looking for, e.g.
>> peak
>> >to peak, rms, etc., though rms jitter is the most common for deriving
a
>> >jitter spec in terms of an ADC (since rms jitter drives ADC noise
>> floor).
>>
>> >>My question really is if the PLL circuit is driven by a clock with a
>> >>jitter x, will the output jitter be x or will it be magnified?
>>
>> >The previous post is about is unambiguous as you can get... it just
>> >depends. :)
>>
>> >Mark
>
>Try some of these application notes and get values from your data
>sheets:
>
>App notes
>
>ADI App Note 501
>http://www.analog.com/UploadedFiles/Application_Notes/6386859756494064912342505447175991257024546937062255921511183854180687755AN501_a.pdf
>
>http://www.analog.com/en/content/0,2886,761%255F795%255F91284%255F0,00.html
>
>http://www.maxim-ic.com/appnotes.cfm/appnote_number/800/
>
>http://gmrt.ncra.tifr.res.in/~scc/BPsamp/Undersamping_&_clk_jitter.pdf
>
>
>Data sheet for
>
>http://www.gaw.ru/pdf/TI/adc/ads5500.pdf
>
>Dale B. Dalrymple
>http://dbdimages.com
>

>Do phase noise and jitter represent the same thing but the first is in
>frequency domain and the second is in time domain?

Sort of, but not necessarily.  Jitter is derived from phase noise, but not
all of your phase noise is typically used to calculate jitter. 
Low-frequency phase noise, for example, is generally assumed as drift, not
jitter, and high frequency phase noise (10s of MHz) probably won't impact
the calculation.  12 kHz - 20 MHz is an often used integration.

>By reviewing the manuals I have, I found a clock skew of 150 ps! To me,
it
>appears to be very high compared with what I am expecting from time
jitter.
>Should I consider the clock skew as a worst case value for jitter. 

NO!  Skew is NOT jitter.  Skew is typically the time difference between
separate output ports in a clock driver, and yes, it will be fixed for a
given part.  It could also mean the delay between input and output, but
that's generally referred to as delay, not skew.  Skew is important when
you're passing data from one part to another, or across clock boundaries in
the same part, each clocked with a separate output from some
clock-distribution scheme.  For 125 MHz data, it is doubtful that a 150 ps
skew will cause much grief.  If it does, you've probably got other timing
issues you need to resolve first.

Note, however, that various digital circuitry can add to your jitter
problem IF it is in-line before the input to your ADC clock.  Good clock
drivers, e.g. ECL/PECL, can have sub-picosecond jitter specs.  I would not
recommend using anything using TTL as a clock source if jitter is a major
concern. :)

Mark

Thank you all for your hints and help. After looking at manuals and
resources that you have given, I would like to confirm with you with the
way that I have calculated the jitter 

1- I got the phase noise curve (dB/Hz) for the 10 MHz reference clock.
This curve is represented by 4 points at 1, 10, 100, 1000 kHz.
2- I have calculated the integrated noise underneath this curve 
3- then I calculated the RMS jitter as described in (Thanks Dale)
http://www.analog.com/en/content/0,2886,760%255F788%255F91502%255F0,00.html

Now this clock is driving the synthesizer from which I am taking my ADC
clock. The transfer function is not available in the data sheet. what
should I look for to know the output jitter from the synthesizer?


>>Do phase noise and jitter represent the same thing but the first is in
>>frequency domain and the second is in time domain?
>
>Sort of, but not necessarily.  Jitter is derived from phase noise, but
not
>all of your phase noise is typically used to calculate jitter. 
>Low-frequency phase noise, for example, is generally assumed as drift,
not
>jitter, and high frequency phase noise (10s of MHz) probably won't
impact
>the calculation.  12 kHz - 20 MHz is an often used integration.
>
>>By reviewing the manuals I have, I found a clock skew of 150 ps! To me,
>it
>>appears to be very high compared with what I am expecting from time
>jitter.
>>Should I consider the clock skew as a worst case value for jitter. 
>
>NO!  Skew is NOT jitter.  Skew is typically the time difference between
>separate output ports in a clock driver, and yes, it will be fixed for a
>given part.  It could also mean the delay between input and output, but
>that's generally referred to as delay, not skew.  Skew is important when
>you're passing data from one part to another, or across clock boundaries
in
>the same part, each clocked with a separate output from some
>clock-distribution scheme.  For 125 MHz data, it is doubtful that a 150
ps
>skew will cause much grief.  If it does, you've probably got other
timing
>issues you need to resolve first.
>
>Note, however, that various digital circuitry can add to your jitter
>problem IF it is in-line before the input to your ADC clock.  Good clock
>drivers, e.g. ECL/PECL, can have sub-picosecond jitter specs.  I would
not
>recommend using anything using TTL as a clock source if jitter is a
major
>concern. :)
>
>Mark
>
>
>

>Thank you all for your hints and help. After looking at manuals and
>resources that you have given, I would like to confirm with you with the
>way that I have calculated the jitter 
>
>1- I got the phase noise curve (dB/Hz) for the 10 MHz reference clock.
>This curve is represented by 4 points at 1, 10, 100, 1000 kHz.
>2- I have calculated the integrated noise underneath this curve 
>3- then I calculated the RMS jitter as described in (Thanks Dale)
>http://www.analog.com/en/content/0,2886,760%255F788%255F91502%255F0,00.html
>
>Now this clock is driving the synthesizer from which I am taking my ADC
>clock. The transfer function is not available in the data sheet. what
>should I look for to know the output jitter from the synthesizer?

If you don't have the transfer function, is it OK for you to provide an
estimate?  If so, go to either www.analog.com or www.national.com and set
up a design session in their online tools.  Pick a part that has properties
that you like (charge pump gain, frequency, etc.) and then plug in the
parameters for your desired output.  Both tools will give you some choices
on the type of filter, and provide a best-case result (depending upon what
you want to optimize for).  Then, once you have the circuit designed, enter
your VCO and reference noise parameters (you might want to get the 10 kHz
noise floor number for the reference, too) and it should give you a proper
analysis.  You can enter the frequency range in the National version which
will provide an rms jitter spec.

Mark