Optimal FFT algorithm for hardware implementation ?

Why not just implement radix-2 FFT algorithm in hardware.
Right now I am implemeting 8 point FFT algorithm in hardware.
I am writing the verilog code. If anyone is interested in 
the code please mail me seperately at bharat at arithos dot com.

In my implementation I have taken care of what Rick has suggested
in his book for reducing multipliers for complex multiplication.

The datain resolution I am assuming is 10 bits, so I have enough
buffer on LSB side. Actually for me the constraint now is to use
only 16x16 multiplier.

Regards
Bharat Pathak