PLL on TMS320C6713 to generate 1Hz output

I am trying to implement a PLL on a board which uses the DSP TMS320C6713
floating point processor.

I am planning to mount a VCXO with a freq range of 1.5 to 77.5 Mhz range
on the board. I have a reference frequency of 10 HZ and I need to generate
a 1HZ  freq as an output. How would you advise me to implement this on the
TI DSP processor.

I do understand that the output of phase detector after passing through
the NCO has to be passed through a D/A converter to give it as input to
VCXO. I am trying to work out a means of generating 1 Hz reference as an
output.

I am also thinking of implementing  it according to the following paper
using counters 

http://www.rt66.com/~shera/QST_GPS.pdf

I am confused should I go the traditional way of having phase detector,
loop filter, NCO   (OR) should I opt the method of counters advised in the 
above paper.

Your advice is greatly appreciated.





 

paryanz wrote:

> I am trying to implement a PLL on a board which uses the DSP TMS320C6713
> floating point processor.
> 
> I am planning to mount a VCXO with a freq range of 1.5 to 77.5 Mhz range
> on the board.

> I have a reference frequency of 10 HZ and I need to generate
> a 1HZ  freq as an output.
> How would you advise me to implement this on the
> TI DSP processor.

Why do you need TMS6713 where something like 74161 would do?

> 
> I do understand that the output of phase detector after passing through
> the NCO has to be passed through a D/A converter to give it as input to
> VCXO. I am trying to work out a means of generating 1 Hz reference as an
> output.
> 
> I am also thinking of implementing  it according to the following paper
> using counters 
> 
> http://www.rt66.com/~shera/QST_GPS.pdf
> 
> I am confused should I go the traditional way of having phase detector,
> loop filter, NCO   (OR) should I opt the method of counters advised in the 
> above paper.
> 
> Your advice is greatly appreciated.

Before going into the minor technical details of CPUs, AD/DA converters 
and other stuff, give the clear and exact definition of the problem: 
what is the input, what is the output, how accurate the output should be.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

I am using a TI6713 because that processor is already in use for the
current application and would like to add a PLL utility to it now.

>Before going into the minor technical details of CPUs, AD/DA converters 
>and other stuff, give the clear and exact definition of the problem: 
>what is the input, what is the output, how accurate the output should
be.

The input is 10 Hz reference freq which is a stable input like a GPS
signal. The output should be a 1 Hz frequency and needs to be pretty
accurate, though I am not aware of any technical terms with accuracy. For
the PLL I am planning to use a VCXO of 1.5 Mz to 77.5 Mhz range. 

>
>
>paryanz wrote:
>
>> I am trying to implement a PLL on a board which uses the DSP
TMS320C6713
>> floating point processor.
>> 
>> I am planning to mount a VCXO with a freq range of 1.5 to 77.5 Mhz
range
>> on the board.
>
>> I have a reference frequency of 10 HZ and I need to generate
>> a 1HZ  freq as an output.
>> How would you advise me to implement this on the
>> TI DSP processor.
>
>Why do you need TMS6713 where something like 74161 would do?
>
>> 
>> I do understand that the output of phase detector after passing
through
>> the NCO has to be passed through a D/A converter to give it as input
to
>> VCXO. I am trying to work out a means of generating 1 Hz reference as
an
>> output.
>> 
>> I am also thinking of implementing  it according to the following
paper
>> using counters 
>> 
>> http://www.rt66.com/~shera/QST_GPS.pdf
>> 
>> I am confused should I go the traditional way of having phase
detector,
>> loop filter, NCO   (OR) should I opt the method of counters advised in
the 
>> above paper.
>> 
>> Your advice is greatly appreciated.
>
>Before going into the minor technical details of CPUs, AD/DA converters 
>and other stuff, give the clear and exact definition of the problem: 
>what is the input, what is the output, how accurate the output should
be.
>
>
>Vladimir Vassilevsky
>DSP and Mixed Signal Design Consultant
>http://www.abvolt.com
>

paryanz wrote:

> I am using a TI6713 because that processor is already in use for the
> current application and would like to add a PLL utility to it now.


> The input is 10 Hz reference freq which is a stable input like a GPS
> signal. The output should be a 1 Hz frequency and needs to be pretty
> accurate, though I am not aware of any technical terms with accuracy. For
> the PLL I am planning to use a VCXO of 1.5 Mz to 77.5 Mhz range. 

Then why PLLs and other crap instead of simply dividing a frequency by 10?

VLV

paryanz wrote:

   ...

> The input is 10 Hz reference freq which is a stable input like a GPS
> signal. The output should be a 1 Hz frequency and needs to be pretty
> accurate, though I am not aware of any technical terms with accuracy. For
> the PLL I am planning to use a VCXO of 1.5 Mz to 77.5 Mhz range. 

I'd like to understand why a simple divide-by-ten won't do.

   ...

Jerry
-- 
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������

Vladimir Vassilevsky wrote:
> 
> 
> paryanz wrote:
> 
>> I am using a TI6713 because that processor is already in use for the
>> current application and would like to add a PLL utility to it now.
> 
> 
>> The input is 10 Hz reference freq which is a stable input like a GPS
>> signal. The output should be a 1 Hz frequency and needs to be pretty
>> accurate, though I am not aware of any technical terms with accuracy. For
>> the PLL I am planning to use a VCXO of 1.5 Mz to 77.5 Mhz range. 
> 
> Then why PLLs and other crap instead of simply dividing a frequency by 10?

Yo mean like an SN7490? :-)

Jerry
-- 
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������

Jerry Avins wrote:

> Vladimir Vassilevsky wrote:
> 
>>
>>
>> paryanz wrote:
>>
>>> I am using a TI6713 because that processor is already in use for the
>>> current application and would like to add a PLL utility to it now.
>>
>>> The input is 10 Hz reference freq which is a stable input like a GPS
>>> signal. The output should be a 1 Hz frequency and needs to be pretty
>>> accurate, though I am not aware of any technical terms with accuracy. 
>>> For the PLL I am planning to use a VCXO of 1.5 Mz to 77.5 Mhz range. 
>>
>>
>> Then why PLLs and other crap instead of simply dividing a frequency by 
>> 10?

How do you like the VCXO with the range of 1.5 to 77.5 MHz? Perhaps it 
is made of liquid crystals.

> 
> Yo mean like an SN7490? :-)

Yoa see, Jerry, it doesn't take the advantage of the efficient 
utilization of streamlined pipelining super scalar hyperthreaded MAC 
parallelism. Besides, there is no function available in Matlab for 
dividing by 10.

> Jerry

VLV

A) 

well regarding the divide by 10...... it looks a real good advice....how
do i implement a simple divide by 10 option. It is a freq divider .... it
is like for every 10 pulses as an input we give 1 pulse out ... I could use
some logic gates....

B)

But truly speaking my reference frequencies are going to be any one of the

following at any given instant not exactly 10Hz

16.8634	16.7224	16.6945	13.7552	12.5628	12.5313	12.0627	11.1483	10.4058	10.0604	10.0402	10.01

I would have to use a PLL or some kind of logic to get a 1 Hz output by
using the above reference frequency. 


Does your advice of using a divider network still be good.

paryanz wrote:
> A) 
> 
> well regarding the divide by 10...... it looks a real good advice....how
> do i implement a simple divide by 10 option. It is a freq divider .... it
> is like for every 10 pulses as an input we give 1 pulse out ... I could use
> some logic gates....
> 
> B)
> 
> But truly speaking my reference frequencies are going to be any one of the
> 
> following at any given instant not exactly 10Hz
> 
> 16.8634	16.7224	16.6945	13.7552	12.5628	12.5313	12.0627	11.1483	10.4058	10.0604	10.0402	10.01
> 
> I would have to use a PLL or some kind of logic to get a 1 Hz output by
> using the above reference frequency. 
> 
> 
> Does your advice of using a divider network still be good.

No.

The posted numbers are familiar. By cross checking with other threads 
you might have written, it is possible that I would have guessed the 
answer to my question. I have other advice for you that will always be 
appropriate: write what you really mean instead of a simplification that 
you hope your readers will be able to expand.

Jerry
-- 
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������

In that thread we were not considering the implementation using C6713 or
some kind of DSP processor and the project requirements were not very clear
to me.

Now I know for sure what hardware I have and what I need to generate, If
you have any specific advice with respect to implementation on a processor
to generate the 1 Hz output with those freqs as a reference input. I would
really appreciate your help.

   Thanks