Hi folks, I manage a hardware engineering group for a telcom company and I am beginning to look around for FPGA IP to implement both FSK modulation and demodulation. I am wondering if any of you have any experience with any of the IP around today. The demodulator is the most difficult part and I believe the following list of requirements is fairly close: * 300 KHz bandwidth * 5-21 MHz frequency range * bit rate = 39.4 KHz * modulation FSK, �f = 75 kHz � 10 KHz, fMark = fc+�f, fSpace = fc-�f The modulator would have similar requirements. Any suggestions would be appreciated. My shop uses both Xilinix and Altera. While we are most comfortable with FPGAs, a DSP would also be a possibility if good software is available. If you think that IP would not be the best choice and another approach would be better, feel free to make a suggestion. Biff
FSK Demodulator
Started by ●July 1, 2008
Reply by ●July 1, 20082008-07-01
biff wrote:> Hi folks, > > I manage a hardware engineering group for a telcom company and I am > beginning to look around for FPGA IP to implement both FSK modulation > and demodulation.I am pretty sure that you are managing homework. Is that right?> I am wondering if any of you have any experience > with any of the IP around today. The demodulator is the most difficult > part and I believe the following list of requirements is fairly close: > > * 300 KHz bandwidth > * 5-21 MHz frequency range > * bit rate = 39.4 KHz > * modulation FSK, �f = 75 kHz � 10 KHz, fMark = fc+�f, fSpace = fc-�f > > The modulator would have similar requirements. Any suggestions would > be appreciated. My shop uses both Xilinix and Altera. While we are > most comfortable with FPGAs, a DSP would also be a possibility if good > software is available. > > If you think that IP would not be the best choice and another approach > would be better, feel free to make a suggestion.All you need is 7474. Convert FSK to baseband and then use 7474 to demodulate it. Don't forget to say "hallo" to the professor.> > BiffVladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●July 1, 20082008-07-01
On Jul 1, 8:43�pm, Vladimir Vassilevsky <antispam_bo...@hotmail.com> wrote:> biff wrote: > > Hi folks, > > > I manage a hardware engineering group for a telcom company and I am > > beginning to look around for FPGA IP to implement both FSK modulation > > and demodulation. > > I am pretty sure that you are managing homework. Is that right? > > > > > I am wondering if any of you have any experience > > with any of the IP around today. �The demodulator is the most difficult > > part �and I believe the following list of requirements is fairly close: > > > * 300 KHz bandwidth > > * 5-21 MHz frequency range > > * bit rate = 39.4 KHz > > * modulation FSK, �f = 75 kHz � 10 KHz, fMark = fc+�f, fSpace = fc-�f > > > The modulator would have similar requirements. Any suggestions would > > be appreciated. My shop uses both Xilinix and Altera. While we are > > most comfortable with FPGAs, a DSP would also be a possibility if good > > software is available. > > > If you think that IP would not be the best choice and another approach > > would be better, feel free to make a suggestion. > > All you need is 7474. Convert FSK to baseband and then use 7474 to > demodulate it. Don't forget to say "hallo" to the professor. > > > > > Biff > > Vladimir Vassilevsky > DSP and Mixed Signal Design Consultanthttp://www.abvolt.comNo homework. My group has no DSP expertise. We normally do data switching. We are using ComBlocks to begin some of the work, but I would feel better about buying some debugged IP. Biff
Reply by ●July 2, 20082008-07-02
biff wrote:> Hi folks, > > I manage a hardware engineering group for a telcom company and I am > beginning to look around for FPGA IP to implement both FSK modulation > and demodulation. I am wondering if any of you have any experience > with any of the IP around today. The demodulator is the most difficult > part and I believe the following list of requirements is fairly close: > > * 300 KHz bandwidth > * 5-21 MHz frequency range > * bit rate = 39.4 KHz > * modulation FSK, �f = 75 kHz � 10 KHz, fMark = fc+�f, fSpace = fc-�f > > The modulator would have similar requirements. Any suggestions would > be appreciated. My shop uses both Xilinix and Altera. While we are > most comfortable with FPGAs, a DSP would also be a possibility if good > software is available. > > If you think that IP would not be the best choice and another approach > would be better, feel free to make a suggestion. > > BiffFSK is pretty easy. This is an elementary enough problem that by the time you finish evaluating IP and integrating it into your design you've spent more money than you would just designing it, or hiring it done custom for you. So I suspect that no one bothers making IP for it. From your specs I gather that you aren't looking for coherent demodulation. Are you looking at a nice clean signal going into the FPGA, or are you coming off of ADCs and wanting to get near-optimal detection? -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" gives you just what it says. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●July 2, 20082008-07-02
On Jul 1, 10:01�pm, Tim Wescott <t...@seemywebsite.com> wrote:> biff wrote: > > Hi folks, > > > I manage a hardware engineering group for a telcom company and I am > > beginning to look around for FPGA IP to implement both FSK modulation > > and demodulation. �I am wondering if any of you have any experience > > with any of the IP around today. The demodulator is the most difficult > > part and I believe the following list of requirements is fairly close: > > > * 300 KHz bandwidth > > * 5-21 MHz frequency range > > * bit rate = 39.4 KHz > > * modulation FSK, �f = 75 kHz � 10 KHz, fMark = fc+�f, fSpace = fc-�f > > > The modulator would have similar requirements. Any suggestions would > > be appreciated. My shop uses both Xilinix and Altera. While we are > > most comfortable with FPGAs, a DSP would also be a possibility if good > > software is available. > > > If you think that IP would not be the best choice and another approach > > would be better, feel free to make a suggestion. > > > Biff > > FSK is pretty easy. �This is an elementary enough problem that by the > time you finish evaluating IP and integrating it into your design you've > spent more money than you would just designing it, or hiring it done > custom for you. > > So I suspect that no one bothers making IP for it.Hiring someone would be an option.> > �From your specs I gather that you aren't looking for coherent > demodulation. �Are you looking at a nice clean signal going into the > FPGA, or are you coming off of ADCs and wanting to get near-optimal > detection?The incoming signal is between 10 and 50 dBmV off of a 75 ohm coaxial cable (cable TV application). In general the SNR is >20 dB. So the signal is large and fairly clean. I am looking for suggestions on what to do. My primary focus right now is getting an estimate of the amount of effort associated with this development so I can put together a proposal. This includes an estimate of the some of the basic FPGA requirements. Things like sample rate, quantization, etc.> > -- > > Tim Wescott > Wescott Design Serviceshttp://www.wescottdesign.com > > Do you need to implement control loops in software? > "Applied Control Theory for Embedded Systems" gives you just what it says. > See details athttp://www.wescottdesign.com/actfes/actfes.html
Reply by ●July 2, 20082008-07-02
biff wrote:> On Jul 1, 10:01 pm, Tim Wescott <t...@seemywebsite.com> wrote: >> biff wrote: >>> Hi folks, >>> I manage a hardware engineering group for a telcom company and I am >>> beginning to look around for FPGA IP to implement both FSK modulation >>> and demodulation. I am wondering if any of you have any experience >>> with any of the IP around today. The demodulator is the most difficult >>> part and I believe the following list of requirements is fairly close: >>> * 300 KHz bandwidth >>> * 5-21 MHz frequency range >>> * bit rate = 39.4 KHz >>> * modulation FSK, �f = 75 kHz � 10 KHz, fMark = fc+�f, fSpace = fc-�f >>> The modulator would have similar requirements. Any suggestions would >>> be appreciated. My shop uses both Xilinix and Altera. While we are >>> most comfortable with FPGAs, a DSP would also be a possibility if good >>> software is available. >>> If you think that IP would not be the best choice and another approach >>> would be better, feel free to make a suggestion. >>> Biff >> FSK is pretty easy. This is an elementary enough problem that by the >> time you finish evaluating IP and integrating it into your design you've >> spent more money than you would just designing it, or hiring it done >> custom for you. >> >> So I suspect that no one bothers making IP for it. > > Hiring someone would be an option. > >> From your specs I gather that you aren't looking for coherent >> demodulation. Are you looking at a nice clean signal going into the >> FPGA, or are you coming off of ADCs and wanting to get near-optimal >> detection? > > The incoming signal is between 10 and 50 dBmV off of a 75 ohm coaxial > cable (cable TV application). In general the SNR is >20 dB. So the > signal is large and fairly clean. I am looking for suggestions on what > to do. My primary focus right now is getting an estimate of the amount > of effort associated with this development so I can put together a > proposal. This includes an estimate of the some of the basic FPGA > requirements. Things like sample rate, quantization, etc. >"Lots". There, isn't that helpful? This is definitely a 'devil's in the details' sort of problem, so whether you need lots of hours, lots of days or lots of weeks depends (ehem) lots on those details. Is the FSK signal to all other energy better than 20dB, or does the FSK signal have to be filtered out from the background? Is the carrier frequency known ahead of time? How close are any other interfering signals? I assume that you'll want to have some sort of sample -> bandpass filter -> heterodyne -> demodulate -> data slice architecture. If you want to do it all digitally and you have to go up to 21MHz that implies sampling well above 42MHz -- 60 would probably be a practical minimum, but you could save money on your anti-aliasing filter by going higher. You'll have a lot of gain in the bandpass filter, so there's a chance that you can do this with a low-bit-count ADC -- the answer to that question depends on more information than you've given, although if the FSK signal were the _only_ signal on the wire then you could do it with a comparator. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" gives you just what it says. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●July 2, 20082008-07-02
On Jul 1, 11:16�pm, Tim Wescott <t...@seemywebsite.com> wrote:> biff wrote: > > On Jul 1, 10:01 pm, Tim Wescott <t...@seemywebsite.com> wrote: > >> biff wrote: > >>> Hi folks, > >>> I manage a hardware engineering group for a telcom company and I am > >>> beginning to look around for FPGA IP to implement both FSK modulation > >>> and demodulation. �I am wondering if any of you have any experience > >>> with any of the IP around today. The demodulator is the most difficult > >>> part and I believe the following list of requirements is fairly close: > >>> * 300 KHz bandwidth > >>> * 5-21 MHz frequency range > >>> * bit rate = 39.4 KHz > >>> * modulation FSK, �f = 75 kHz � 10 KHz, fMark = fc+�f, fSpace = fc-�f > >>> The modulator would have similar requirements. Any suggestions would > >>> be appreciated. My shop uses both Xilinix and Altera. While we are > >>> most comfortable with FPGAs, a DSP would also be a possibility if good > >>> software is available. > >>> If you think that IP would not be the best choice and another approach > >>> would be better, feel free to make a suggestion. > >>> Biff > >> FSK is pretty easy. �This is an elementary enough problem that by the > >> time you finish evaluating IP and integrating it into your design you've > >> spent more money than you would just designing it, or hiring it done > >> custom for you. > > >> So I suspect that no one bothers making IP for it. > > > Hiring someone would be an option. > > >> �From your specs I gather that you aren't looking for coherent > >> demodulation. �Are you looking at a nice clean signal going into the > >> FPGA, or are you coming off of ADCs and wanting to get near-optimal > >> detection? > > > The incoming signal is between 10 and 50 dBmV off of a 75 ohm coaxial > > cable (cable TV application). In general the SNR is >20 dB. So the > > signal is large and fairly clean. I am looking for suggestions on what > > to do. My primary focus right now is getting an estimate of the amount > > of effort associated with this development so I can put together a > > proposal. This includes an estimate of the some of the basic FPGA > > requirements. Things like sample rate, quantization, etc. > > "Lots". �There, isn't that helpful? �This is definitely a 'devil's in > the details' sort of problem, so whether you need lots of hours, lots of > days or lots of weeks depends (ehem) lots on those details. > > Is the FSK signal to all other energy better than 20dB, or does the FSK > signal have to be filtered out from the background?There are other signals on the coax, but analog filters (a diplexer and passive filter) will filter them out before they get to this hardware.>�Is the carrier > frequency known ahead of time? �We will know the carrier ahead of time. An enhancement in the future would make the carrier programmable, but this feature would not be needed initially. I would like the FPGA to be sized to support this as a future feature.>How close are any other interfering signals? > > I assume that you'll want to have some sort of sample -> bandpass filter > -> heterodyne -> demodulate -> data slice architecture.That is what I put in my initial concept proposal. Remember my only formal DSP training was 25 years ago. I am an analog circuit designer by training.>�If you want to > do it all digitally and you have to go up to 21MHz that implies sampling > well above 42MHz -- 60 would probably be a practical minimum, but you > could save money on your anti-aliasing filter by going higher. �You'll > have a lot of gain in the bandpass filter, so there's a chance that you > can do this with a low-bit-count ADC -- the answer to that question > depends on more information than you've given, although if the FSK > signal were the _only_ signal on the wire then you could do it with a > comparator.At this point, the only signal in that band is the FSK signal. What I put in my proposal was * analog front (RF diplexer, filter, amplifier) * A/D converter * numerical oscillator for mixing * detector My assumption was that I could mix the signal down (possibly flip the spectrum) so that my space symbol is at DeltaF and my mark symbol is at 0 Hz (DC). I can then filter the DeltaF out with a low-pass filter, leaving me with the bit stream. I have Matlab and I have started to play with simulation. It seemed to work. It seemed too simple.> > -- > > Tim Wescott > Wescott Design Serviceshttp://www.wescottdesign.com > > Do you need to implement control loops in software? > "Applied Control Theory for Embedded Systems" gives you just what it says. > See details athttp://www.wescottdesign.com/actfes/actfes.html
Reply by ●July 2, 20082008-07-02
biff wrote:> On Jul 1, 11:16 pm, Tim Wescott <t...@seemywebsite.com> wrote: >> biff wrote: >>> On Jul 1, 10:01 pm, Tim Wescott <t...@seemywebsite.com> wrote: >>>> biff wrote: >>>>> Hi folks, >>>>> I manage a hardware engineering group for a telcom company and I am >>>>> beginning to look around for FPGA IP to implement both FSK modulation >>>>> and demodulation. I am wondering if any of you have any experience >>>>> with any of the IP around today. The demodulator is the most difficult >>>>> part and I believe the following list of requirements is fairly close: >>>>> * 300 KHz bandwidth >>>>> * 5-21 MHz frequency range >>>>> * bit rate = 39.4 KHz >>>>> * modulation FSK, �f = 75 kHz � 10 KHz, fMark = fc+�f, fSpace = fc-�f >>>>> The modulator would have similar requirements. Any suggestions would >>>>> be appreciated. My shop uses both Xilinix and Altera. While we are >>>>> most comfortable with FPGAs, a DSP would also be a possibility if good >>>>> software is available. >>>>> If you think that IP would not be the best choice and another approach >>>>> would be better, feel free to make a suggestion. >>>>> Biff >>>> FSK is pretty easy. This is an elementary enough problem that by the >>>> time you finish evaluating IP and integrating it into your design you've >>>> spent more money than you would just designing it, or hiring it done >>>> custom for you. >>>> So I suspect that no one bothers making IP for it. >>> Hiring someone would be an option. >>>> From your specs I gather that you aren't looking for coherent >>>> demodulation. Are you looking at a nice clean signal going into the >>>> FPGA, or are you coming off of ADCs and wanting to get near-optimal >>>> detection? >>> The incoming signal is between 10 and 50 dBmV off of a 75 ohm coaxial >>> cable (cable TV application). In general the SNR is >20 dB. So the >>> signal is large and fairly clean. I am looking for suggestions on what >>> to do. My primary focus right now is getting an estimate of the amount >>> of effort associated with this development so I can put together a >>> proposal. This includes an estimate of the some of the basic FPGA >>> requirements. Things like sample rate, quantization, etc. >> "Lots". There, isn't that helpful? This is definitely a 'devil's in >> the details' sort of problem, so whether you need lots of hours, lots of >> days or lots of weeks depends (ehem) lots on those details. >> >> Is the FSK signal to all other energy better than 20dB, or does the FSK >> signal have to be filtered out from the background? > > There are other signals on the coax, but analog filters (a diplexer > and passive filter) will filter them out before they get to this > hardware. > >> Is the carrier >> frequency known ahead of time? > > We will know the carrier ahead of time. An enhancement in the future > would make the carrier programmable, but this feature would not be > needed initially. I would like the FPGA to be sized to support this as > a future feature. > >> How close are any other interfering signals? >> >> I assume that you'll want to have some sort of sample -> bandpass filter >> -> heterodyne -> demodulate -> data slice architecture. > > That is what I put in my initial concept proposal. Remember my only > formal DSP training was 25 years ago. I am an analog circuit designer > by training. > >> If you want to >> do it all digitally and you have to go up to 21MHz that implies sampling >> well above 42MHz -- 60 would probably be a practical minimum, but you >> could save money on your anti-aliasing filter by going higher. You'll >> have a lot of gain in the bandpass filter, so there's a chance that you >> can do this with a low-bit-count ADC -- the answer to that question >> depends on more information than you've given, although if the FSK >> signal were the _only_ signal on the wire then you could do it with a >> comparator. > > At this point, the only signal in that band is the FSK signal. What I > put in my proposal was > > * analog front (RF diplexer, filter, amplifier) > * A/D converter > * numerical oscillator for mixing > * detector > > My assumption was that I could mix the signal down (possibly flip the > spectrum) so that my space symbol is at DeltaF and my mark symbol is > at 0 Hz (DC). I can then filter the DeltaF out with a low-pass filter, > leaving me with the bit stream. > > I have Matlab and I have started to play with simulation. It seemed to > work. It seemed too simple. >I think it is. In general your mark symbol will be close to 0Hz but not right on (unless you control the exact amount of the delta), and it will be the sine of some random phase. You can improve this by mixing with an inphase and quadrature mixer so that you'll always see energy at DC. Rejecting the space symbol and keeping the mark makes you much more sensitive to noise -- a system that detects each one then compares the relative strength is much more robust in the face of noise and varying signal strengths. You can get this effect by either demodulating with four mixers, or by extracting the high-pass side from your low-pass filter and using that for the other side of your comparison. This seems to be a better fit to analog circuitry than to an FPGA. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" gives you just what it says. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●July 2, 20082008-07-02
On Jul 2, 12:43�am, Tim Wescott <t...@seemywebsite.com> wrote:> biff wrote: > > On Jul 1, 11:16 pm, Tim Wescott <t...@seemywebsite.com> wrote: > >> biff wrote: > >>> On Jul 1, 10:01 pm, Tim Wescott <t...@seemywebsite.com> wrote: > >>>> biff wrote: > >>>>> Hi folks, > >>>>> I manage a hardware engineering group for a telcom company and I am > >>>>> beginning to look around for FPGA IP to implement both FSK modulation > >>>>> and demodulation. �I am wondering if any of you have any experience > >>>>> with any of the IP around today. The demodulator is the most difficult > >>>>> part and I believe the following list of requirements is fairly close: > >>>>> * 300 KHz bandwidth > >>>>> * 5-21 MHz frequency range > >>>>> * bit rate = 39.4 KHz > >>>>> * modulation FSK, �f = 75 kHz � 10 KHz, fMark = fc+�f, fSpace = fc-�f > >>>>> The modulator would have similar requirements. Any suggestions would > >>>>> be appreciated. My shop uses both Xilinix and Altera. While we are > >>>>> most comfortable with FPGAs, a DSP would also be a possibility if good > >>>>> software is available. > >>>>> If you think that IP would not be the best choice and another approach > >>>>> would be better, feel free to make a suggestion. > >>>>> Biff > >>>> FSK is pretty easy. �This is an elementary enough problem that by the > >>>> time you finish evaluating IP and integrating it into your design you've > >>>> spent more money than you would just designing it, or hiring it done > >>>> custom for you. > >>>> So I suspect that no one bothers making IP for it. > >>> Hiring someone would be an option. > >>>> �From your specs I gather that you aren't looking for coherent > >>>> demodulation. �Are you looking at a nice clean signal going into the > >>>> FPGA, or are you coming off of ADCs and wanting to get near-optimal > >>>> detection? > >>> The incoming signal is between 10 and 50 dBmV off of a 75 ohm coaxial > >>> cable (cable TV application). In general the SNR is >20 dB. So the > >>> signal is large and fairly clean. I am looking for suggestions on what > >>> to do. My primary focus right now is getting an estimate of the amount > >>> of effort associated with this development so I can put together a > >>> proposal. This includes an estimate of the some of the basic FPGA > >>> requirements. Things like sample rate, quantization, etc. > >> "Lots". �There, isn't that helpful? �This is definitely a 'devil's in > >> the details' sort of problem, so whether you need lots of hours, lots of > >> days or lots of weeks depends (ehem) lots on those details. > > >> Is the FSK signal to all other energy better than 20dB, or does the FSK > >> signal have to be filtered out from the background? > > > There are other signals on the coax, but analog filters (a diplexer > > and passive filter) will filter them out before they get to this > > hardware. > > >> �Is the carrier > >> frequency known ahead of time? � > > > We will know the carrier ahead of time. An enhancement in the future > > would make the carrier programmable, but this feature would not be > > needed initially. I would like the FPGA to be sized to support this as > > a future feature. > > >> How close are any other interfering signals? > > >> I assume that you'll want to have some sort of sample -> bandpass filter > >> -> heterodyne -> demodulate -> data slice architecture. > > > That is what I put in my initial concept proposal. Remember my only > > formal DSP training was 25 years ago. I am an analog circuit designer > > by training. > > >> �If you want to > >> do it all digitally and you have to go up to 21MHz that implies sampling > >> well above 42MHz -- 60 would probably be a practical minimum, but you > >> could save money on your anti-aliasing filter by going higher. �You'll > >> have a lot of gain in the bandpass filter, so there's a chance that you > >> can do this with a low-bit-count ADC -- the answer to that question > >> depends on more information than you've given, although if the FSK > >> signal were the _only_ signal on the wire then you could do it with a > >> comparator. > > > At this point, the only signal in that band is the FSK signal. What I > > put in my proposal was > > > * analog front (RF diplexer, filter, amplifier) > > * A/D converter > > * numerical oscillator for mixing > > * detector > > > My assumption was that I could mix the signal down (possibly flip the > > spectrum) so that my space symbol �is at DeltaF and my mark symbol �is > > at 0 Hz (DC). I can then filter the DeltaF out with a low-pass filter, > > leaving me with the bit stream. > > > I have Matlab and I have started to play with simulation. It seemed to > > work. It seemed too simple. > > I think it is. > > In general your mark symbol will be close to 0Hz but not right on > (unless you control the exact amount of the delta), and it will be the > sine of some random phase. �You can improve this by mixing with an > inphase and quadrature mixer so that you'll always see energy at DC. > > Rejecting the space symbol and keeping the mark makes you much more > sensitive to noise -- a system that detects each one then compares the > relative strength is much more robust in the face of noise and varying > signal strengths. �You can get this effect by either demodulating with > four mixers, or by extracting the high-pass side from your low-pass > filter and using that for the other side of your comparison. > > This seems to be a better fit to analog circuitry than to an FPGA. > > -- > > Tim Wescott > Wescott Design Serviceshttp://www.wescottdesign.com > > Do you need to implement control loops in software? > "Applied Control Theory for Embedded Systems" gives you just what it says. > See details athttp://www.wescottdesign.com/actfes/actfes.htmlIt seems like I will end up with essentially two matched filters and then I make a decision based on the relative output. Correct? Biff
Reply by ●July 2, 20082008-07-02
biff wrote:> It seems like I will end up with essentially two matched filters and > then I make a decision based on the relative output. > Correct?The belowmentioned method is not the very optimal, however it is very simple and it does the job: 1. Convert your signal to the baseband (I,Q) by multiplying by sin() and cos() of the center frequency and lopassing the result. * You can get by the square wave representation of sin/cos (it depends). * Exponential averager or moving averager or CIC filter for lowpasing is probably OK (it depends). 2. Apply I to the D input of flipflop, Q to the C input of the flipflop. The output of the flipflop is the demodulated FSK. * You can make better discriminator from two flipflops and some logic (using the same idea). * You may have to apply some filtering/slicing/synchronization logic after the discriminator (it depends). 3. That's about it. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
