Forums

AW: DSP56303: max clock speed

Started by Bende Georg June 5, 2003
The processor executes one instruction per 2 clock cycles; this makes with 200
MHz 100 MIPS. So both manuals are correct.

Best regards,
Georg Bende
Softwareentwickler
Abteilung Elektronik
Dr. Fritz Faulhaber GmbH & Co KG
Daimlerstr. 23
71101 Schaich
Tel: +49 7031 638294

> -----Ursprgliche Nachricht-----
> Von: GuillaumeDesj [mailto:]
> Gesendet: Donnerstag, 5. Juni 2003 00:17
> An:
> Betreff: [motoroladsp] DSP56303: max clock speed
>
> The DSP56303 user's manual says that ...
> "The DSP56303 offers 100 million instructions per second (MIPS)
> performance using an internal 100 MHz"
>
> However if you look at the datasheet (paragraph 2.6.3), the value
> listed for maximum frequency of the VCO with PLL Enabled is of 200Mhz.
>
> Is it possible to run the DSP56303 at 200Mhz ? or will the PLL start
> acting crazy if the registers are programmed that way ? >
> _____________________________________
> Note: If you do a simple "reply" with your email client, only the author
> of this message will receive your answer. You need to do a "reply all" if
> you want your answer to be distributed to the entire group.
>
> _____________________________________
> About this discussion group:
>
> To Join:
>
> To Post:
>
> To Leave:
>
> Archives: http://www.yahoogroups.com/group/motoroladsp
>
> More Groups: http://www.dsprelated.com/groups.php3 > ">http://docs.yahoo.com/info/terms/
>



The 56300 Family does NOT require two clock cycles per instruction. It
is a single cycle per instruction machine. The predicesor of the 56300,
the 56000 Family requires two clocks per instruction. If you look at
the PLL block diagram (Figure 6-2) and the Clkgen diagram (Figure 6-3)
in the Family Manual you'll see that the VCO actually operates at twice
the core clock frequency to make up for the final divide by 2 shown in
Figure 6-3. This is all transparent to the user, who configures the PLL
register for the core frequency desired. In other words, when you have
configured the PCTL register for 100MHz operation, the VCO will be
operating at 200MHz. Since the 56300 Family is a single cycle machine,
this provides 100MIPS of execution power...

--
dB

--- Bende Georg <> wrote:
> The processor executes one instruction per 2 clock cycles; this makes
> with 200 MHz 100 MIPS. So both manuals are correct.
>
> Best regards,
> Georg Bende
> Softwareentwickler
> Abteilung Elektronik
> Dr. Fritz Faulhaber GmbH & Co KG
> Daimlerstr. 23
> 71101 Schaich
> Tel: +49 7031 638294
>
> > -----Ursprgliche Nachricht-----
> > Von: GuillaumeDesj [mailto:]
> > Gesendet: Donnerstag, 5. Juni 2003 00:17
> > An:
> > Betreff: [motoroladsp] DSP56303: max clock speed
> >
> > The DSP56303 user's manual says that ...
> > "The DSP56303 offers 100 million instructions per second (MIPS)
> > performance using an internal 100 MHz"
> >
> > However if you look at the datasheet (paragraph 2.6.3), the value
> > listed for maximum frequency of the VCO with PLL Enabled is of
> 200Mhz.
> >
> > Is it possible to run the DSP56303 at 200Mhz ? or will the PLL
> start
> > acting crazy if the registers are programmed that way ?
> >
> >
> >
> > _____________________________________
> > Note: If you do a simple "reply" with your email client, only the
> author
> > of this message will receive your answer. You need to do a "reply
> all" if
> > you want your answer to be distributed to the entire group.
> >
> > _____________________________________
> > About this discussion group:
> >
> > To Join:
> >
> > To Post:
> >
> > To Leave:
> >
> > Archives: http://www.yahoogroups.com/group/motoroladsp
> >
> > More Groups: http://www.dsprelated.com/groups.php3
> >
> >
> > ">http://docs.yahoo.com/info/terms/
> >


__________________________________