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Understanding quad timer

Started by TA1T June 24, 2003

Can someone help me understand how to calculate what frequency is
output from the quad timer. After playing around with numbers i
eventually came up with the following solution to obtain a 10KHz
square wave, but dont know how this could have been calculated. I set the PLL_DIVIDE_BY REG in appconfig.h to 0x00B0 I then used these parameters in main function

const qt_sState quadParam1 = {

/* Mode = */ qtCount,
/* InputSource = */ qtPrescalerDiv1,
/* InputPolarity = */ qtNormal,
/* SecondaryInputSource = */ 0,

/* CountFrequency = */ qtRepeatedly,
/* CountLength = */ qtUntilCompare,
/* CountDirection = */ qtUp,

/* OutputMode = */ qtToggleOnCompare,
/* OutputPolarity = */ qtNormal,
/* OutputDisabled = */ 0,

/* Master = */ 0,
/* OutputOnMaster = */ 0,
/* CoChannelInitialize = */ 0,
/* AssertWhenForced = */ 0,

/* CaptureMode = */ qtDisabled,

/* CompareValue1 = */ 0x977, //generates 10KHz
/* CompareValue2 = */ 0,
/* InitialLoadValue = */ 0,

/* CallbackOnCompare = */ { 0, 0 },
/* CallbackOnOverflow = */ { 0, 0 },
/* CallbackOnInputEdge = */ { 0, 0 }
}; Why have these settings generated a 10KHZ clock?



Hi CJ,

It's not real easy.

The first question I would ask is where you came up with the value of
0x00B0 for the pll divide reg. From what I can see that value will
put the PLL at a frequency that is way beyond it's recommended
operating parameters (See DSP56F80X User's Manual, Chapter 15 On Chip
Clock Synthesis, Section 15.6.12).

To run the normal 80MHz frequency a value of 0x0013 (19) would be
used in the PLL divide reg. This gives a 40MHz IP_BUS frequency
which drives the quad timer inputs. It is calculated by
(8MHz * (19+1) / 2 / 2)= IP_BUS freq. or
(crystal * (PLLDB+1) / Div2 / Div2)= IP_BUS freq.
Figure 15-14 shows a good layout of how that is derived.

When you know your input frequency (IP_BUS) you can set the values in
the qt_sState structure to get your desired freq.
-With qtPrescalerDiv1 you still have IP_BUS (40MHz if using 19)
clocking the timer.
-Using 'toggle on compare' (qtRepeatedly, qtUntilCompare,
qtToggleOnCompare, qtUp) your output frequency will be 1/2 the toggle
frequency which is the input freq divided by the compare value OR
(IP_BUS / CompareValue1 / 2) = Output Freq.
(40MHz / 2000 / 2) = 10khz

Hope this Helps.

Pete

--- In , "TA1T" <cj_tait@h...> wrote:
>
> Can someone help me understand how to calculate what frequency is
> output from the quad timer. After playing around with numbers i
> eventually came up with the following solution to obtain a 10KHz
> square wave, but dont know how this could have been calculated. > I set the PLL_DIVIDE_BY REG in appconfig.h to 0x00B0 > I then used these parameters in main function
>
> const qt_sState quadParam1 = {
>
> /* Mode = */ qtCount,
> /* InputSource = */ qtPrescalerDiv1,
> /* InputPolarity = */ qtNormal,
> /* SecondaryInputSource = */ 0,
>
> /* CountFrequency = */ qtRepeatedly,
> /* CountLength = */ qtUntilCompare,
> /* CountDirection = */ qtUp,
>
> /* OutputMode = */ qtToggleOnCompare,
> /* OutputPolarity = */ qtNormal,
> /* OutputDisabled = */ 0,
>
> /* Master = */ 0,
> /* OutputOnMaster = */ 0,
> /* CoChannelInitialize = */ 0,
> /* AssertWhenForced = */ 0,
>
> /* CaptureMode = */ qtDisabled,
>
> /* CompareValue1 = */ 0x977, //generates 10KHz
> /* CompareValue2 = */ 0,
> /* InitialLoadValue = */ 0,
>
> /* CallbackOnCompare = */ { 0, 0 },
> /* CallbackOnOverflow = */ { 0, 0 },
> /* CallbackOnInputEdge = */ { 0, 0 }
> }; > Why have these settings generated a 10KHZ clock?