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'826 - when interrupts are active - Software is loosing it....

Started by bmbmz123 July 14, 2003
Hello,

Without interupts, sw is running ok.

When I apply the interupts (archEnableInt), the sw is doing crazy
stuff - some of the data is overrun, code sections are executed even
though it is not supposed to.

But, the sw is alive, doing other things it is supposed to!!
It behaves as if some code lines are ignored!

Has anyone met this before? Any ideas why?

10x
boaz



Hello,

Without interupts, sw is running ok.

When I apply the interupts (archEnableInt), the sw is doing crazy
stuff - some of the data is overrun, code sections are executed even
though it is not supposed to.

But, the sw is alive, doing other things it is supposed to!!
It behaves as if some code lines are ignored!

Has anyone met this before? Any ideas why?

10x
boaz



I am trying to understand the data that is in the books concerning
interrupts on the 56805.

I am trying to disable all (software/hardware) interrupts by modifying the
SR register. In the User's Manual, page 4-3, it says, "To permit mask
exceptions, I bits (in the SR reg) should be set to 01. To disable mask
exceptions, I bits should be set to 11."

Now the confusion starts when I go to the DSP Family Manual for the
56805 and look at the description of the SR register. It says in Table
5-1 that when I bits is:

Ibits Exceptions Permitted Exceptions Masked
01 IPL 0,1 None
11 IPL 1 IPL 0

When Ibits is set to 11 it still permits IPL1 which contradicts the User
Manual which says it will disable mask exceptions.

What am I not understading?



Hi Mark

IPL 1 describes Non-Maskable Interrupts (NMI). I would not have said "to
disable mask exceptions", I would have said "to disable maskABLE
exceptions". Grammar is our friend, Motorola notwithstanding.

I used to get confused between (on the one hand):
Status Register IPLs (Interrupt Priority Level 0 and 1), which seem
only to be maskable -vs- non-maskable,
and, on the other hand:
ITCN PLRs (Priority Level Registers 0 through 7) which are what I
would have called "interrupt priorities".

Why the Family manual dwells at length on simulating interrupt priorities in
software is a mystery that will probably forever be beyond my grasp. Did
early versions of the chips lack working ITCN PLRs?

Rick Corey -----Original Message-----
From: [mailto:]
Sent: Thursday, August 07, 2003 10:29 AM
To:
Cc:
Subject: [motoroladsp] Interrupts (masking them all) - 56805
I am trying to understand the data that is in the books concerning
interrupts on the 56805.

I am trying to disable all (software/hardware) interrupts by modifying the
SR register. In the User's Manual, page 4-3, it says, "To permit mask
exceptions, I bits (in the SR reg) should be set to 01. To disable mask
exceptions, I bits should be set to 11."

Now the confusion starts when I go to the DSP Family Manual for the
56805 and look at the description of the SR register. It says in Table
5-1 that when I bits is:

Ibits Exceptions Permitted Exceptions Masked
01 IPL 0,1 None
11 IPL 1 IPL 0

When Ibits is set to 11 it still permits IPL1 which contradicts the User
Manual which says it will disable mask exceptions.

What am I not understading?
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RE: [motoroladsp] Interrupts (masking them all) - 56805

It is my understanding that there is a distintion between "mask exceptions" and the external interrupts.  Mask Exceptions are all interrupts that can be masked by a privledge level mask bit.

Since external interrupts are not by nature maskable, but can be enabled or disabled with other bits, there operation is not covered by the bit in question, whereas the other host of interrupts are enabled when the bits are 01, and disabled when the bits are 11.

I hope my interpretation is correct, and does not lead to further confusion.

Jerry.

-----Original Message-----
From: m...@bish.net [mailto:m...@bish.net]
Sent: Thursday, August 07, 2003 9:29 AM
To: m...@yahoogroups.com
Cc: m...@yahoogroups.com
Subject: [motoroladsp] Interrupts (masking them all) - 56805



I am trying to understand the data that is in the books concerning
interrupts on the 56805.

I am trying to disable all (software/hardware) interrupts by modifying the
SR register.  In the User's Manual, page 4-3, it says, "To permit mask
exceptions, I bits (in the SR reg) should be set to 01. To disable mask
exceptions, I bits should be set to 11."

Now the confusion starts when I go to the DSP Family Manual for the
56805 and look at the description of the SR register.  It says in Table
5-1 that when I bits is:

Ibits   Exceptions Permitted    Exceptions Masked
01      IPL 0,1                 None
11      IPL 1                   IPL 0

When Ibits is set to 11 it still permits IPL1 which contradicts the User
Manual which says it will disable mask exceptions.

What am I not understading?


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RE: [motoroladsp] Interrupts (masking them all) - 56805
Hi Jerry
 
I think the external IRQs IRQA and IRQB are maskable by setting SR:I-bits (page 4-4, section 4.2 of my 5680x User's Manual, Rev.2).
 
My old copy of the Family manual gives some IPL 0  interrupts (NMI?) on page 7-11, section 7.4.2, Table 7-4:
    Hardware Reset
    COP
    Illegal Instruction Trap
    SWI
    Hardware Stack Overflow
    OnCE Trap
 
It lists IRQA and IRQB as IPL 0 like every on-chip peripheral IRQ, whereas the 6 I listed as NMI are stated as being IPL 1.
 
I see what you're saying about IRQA and IRQB not being controlled by an ITCN PLR. 
Table 4.2 in the 5680x UM shows them as "controlled directly by the DSP core", not the ITCN module. 
 
Rick Corey
-----Original Message-----
From: Johnson, Jerry [mailto:j...@giddings.com]
Sent: Thursday, August 07, 2003 11:09 AM
To: 'm...@bish.net'; 'm...@yahoogroups.com'
Subject: RE: [motoroladsp] Interrupts (masking them all) - 56805

It is my understanding that there is a distintion between "mask exceptions" and the external interrupts.  Mask Exceptions are all interrupts that can be masked by a privledge level mask bit.

Since external interrupts are not by nature maskable, but can be enabled or disabled with other bits, there operation is not covered by the bit in question, whereas the other host of interrupts are enabled when the bits are 01, and disabled when the bits are 11.

I hope my interpretation is correct, and does not lead to further confusion.

Jerry.

-----Original Message-----
From: m...@bish.net [mailto:m...@bish.net]
Sent: Thursday, August 07, 2003 9:29 AM
To: m...@yahoogroups.com
Cc: m...@yahoogroups.com
Subject: [motoroladsp] Interrupts (masking them all) - 56805



I am trying to understand the data that is in the books concerning
interrupts on the 56805.

I am trying to disable all (software/hardware) interrupts by modifying the
SR register.  In the User's Manual, page 4-3, it says, "To permit mask
exceptions, I bits (in the SR reg) should be set to 01. To disable mask
exceptions, I bits should be set to 11."

Now the confusion starts when I go to the DSP Family Manual for the
56805 and look at the description of the SR register.  It says in Table
5-1 that when I bits is:

Ibits   Exceptions Permitted    Exceptions Masked
01      IPL 0,1                 None
11      IPL 1                   IPL 0

When Ibits is set to 11 it still permits IPL1 which contradicts the User
Manual which says it will disable mask exceptions.

What am I not understading?


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After going back and forth between the Family Manual and the User's Guide
I think I have it. Section 7.3.X in the Family Manual should have been
put into the User's Guide - I was unaware that there were two priorities
of interrupts and that only one of those two priorities was maskable,
which makes complete sense. But I only read the User's Guide which
doesn't have any information about the non-maskable interrupts.

Guess I made too many assuptions. Thanks for the replies, they helped.


On Thu, 7 Aug 2003, Corey, Rick wrote:

> Hi Mark
>
> IPL 1 describes Non-Maskable Interrupts (NMI). I would not have said "to
> disable mask exceptions", I would have said "to disable maskABLE
> exceptions". Grammar is our friend, Motorola notwithstanding.

Yeah, that's how it came right out of the book.

>
> I used to get confused between (on the one hand):
> Status Register IPLs (Interrupt Priority Level 0 and 1), which seem
> only to be maskable -vs- non-maskable,
> and, on the other hand:
> ITCN PLRs (Priority Level Registers 0 through 7) which are what I
> would have called "interrupt priorities".
>

That's what caused my confusion and only going back and forth between the
two manuals was I able to clear up my own misunderstanding.


On Thu, 7 Aug 2003, Corey, Rick wrote:

> Hi Jerry
>
> I think the external IRQs IRQA and IRQB are maskable by setting SR:I-bits
> (page 4-4, section 4.2 of my 5680x User's Manual, Rev.2).

Yes, that's how I am masking them - but when you do that you mask all
level 0 interrupts (which include all on-chip peripherals, timers, serial
ports, etc)


The IRQA and IRQB can be individually controlled using the IBL and IAL bit fields in the IPR. Using these bits the IRQA and IRQB can be individually masked. The IPR also allows for masking and unmasking of the different priority level interrupts by manipulating the CH0 through CH6 bits. 
 
The discussions on this subject between the Family manual and the user manual are confusing. The family manual explains how the 56800 core operates. The 56F80x user manual  details the 56F80x peripherals. The ITCN is a chip peripheral and not part of the 56800 core. The 56800 core has several interrupt sources that it recognizes. These are the Hardware Reset, COP Watchdog Reset, Illegal Instruction Trap, SWI, Hardware Stack Overflow, IRQA, RQB, and the chanel 0 through 6 interrupts. The 56800 core is fully responsible for recognizing and altering the program flow of the core to service these interupt sources.
 
The ITCN controls and manages the peripheral interrupt signals and requests interrupt services from the 56800 core. It requests the interrupt services by using the core CH0-CH6 interrupt signals. These are the signals that are controlled in the IPR. At any given clock cycle the ITCN scans the input interrupt signals from the peripherals and determines if a specifc peripheral is requesting an interrupt and what is the highest priority interrupt request is and it in turn uses the appropriate CHX signal to request an interrupt from the 56800 core. The ITCN will also provide an ISR vector to the core.
 
The IPR and SR are core registers. The SR bits I0 and I1 bits control whether the core maskable interrupt sources are masked or unmasked. The peripheral interrupt sources are also globally masked and unmasked since the ITCN uses the CH0-CH6 core interrupt signals to request interrupt services from the core. The Family manual in chapter 7 describes how the core handles interrupts. This material is not in the user manual because the user manual only has material on the chip peripherals and the chip integration.
 
Hope this helps on giving some back ground on what is going on. Thanks.

[Hutchings William-p23437]  -----Original Message-----
From: m...@bish.net [mailto:m...@bish.net]
Sent: Thursday, August 07, 2003 8:52 AM
To: Corey, Rick
Cc: 'Johnson, Jerry'; m...@yahoogroups.com
Subject: RE: [motoroladsp] Interrupts (masking them all) - 56805

On Thu, 7 Aug 2003, Corey, Rick wrote:

> Hi Jerry
>
> I think the external IRQs IRQA and IRQB are maskable by setting SR:I-bits
> (page 4-4, section 4.2 of my 5680x User's Manual, Rev.2).

Yes, that's how I am masking them - but when you do that you mask all
level 0 interrupts (which include all on-chip peripherals, timers, serial
ports, etc)


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